AP0100CS datasheet(4/73 Pages) ONSEMI

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AP0100CS HDR: Image Signal Processor (ISP)

General Description

AP0100CS/D Rev. 6, Pub. 1/16 EN

©Semiconductor Components Industries, LLC,2016.

General Description

The ON Semiconductor AP0100CS is a high-performance, ultra-low power in-line,

digital image processor optimized for use with HDR (High Dynamic Range) sensors. The

AP0100CS provides full auto-functions support (AWB and AE) and ALTM (Adaptive Local

Tone Mapping) to enhance HDR images and advanced noise reduction which enables

excellent low-light performance.

Functional Overview

Figure 1 shows the typical configuration of the AP0100CS in a camera system. On the

host side, a two-wire serial interface is used to control the operation of the AP0100CS,

and image data is transferred using the analog or parallel interface between the

AP0100CS and the host. The AP0100CS interface to the sensor also uses a parallel inter-

face.

Figure 1:

AP0100CS Connectivity

System Interfaces

Figure 2: “Typical Parallel Configuration,” on page 5 and Figure 3: “Typical HiSPi Config-

uration,” on page 6 show typical AP0100CS device connections.

All power supply rails must be decoupled from ground using capacitors as close as

possible to the package.

The AP0100CS signals to the sensor and host interfaces can be at different supply voltage

levels to optimize power consumption and maximize flexibility. Table 1 on page 9

provides the signal descriptions for the AP0100CS.

1.2Mp HDR Sensor

12-bit parallel

Host

Two-wire serial I/F (CCIM)

Two-wire serial IF (CCIS)

Two-lane HiSPi

Analog

NTSC/PAL display

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