AP0101CS datasheet(15/42 Pages) ONSEMI

15 / 42 page

AP0101CS/D Rev. 7, 1/16 EN

©Semiconductor Components Industries, LLC,2016.

AP0101CS HDR: Image Signal Processor (ISP)

Image Flow Processor

The second mode supported is called 'continuous'; this is when a trigger pulse will cause

the part to continuously output frames, see Figure 8. This mode would be especially

useful for applications which have multiple sensors and need to have their video

streams synchronized (for example, surround view or panoramic view applications).

Figure 8:

Continuous Mode

Note:

This diagram is not to scale.

When two or more cameras have a signal applied to the FRAME_SYNC input at the same

time, the respective FV_OUT signals would be synchronized within 5 PIXCLK_OUT

cycles. This assumes that all cameras have the same configuration settings and that the

exposure time is the same.

Image Flow Processor

Image and color processing in the AP0101CS is implemented as an image flow processor

(IFP) coded in hardware logic. During normal operation, the embedded microcontroller

will automatically adjust the operating parameters. For normal operation of the

AP0101CS, a stream of raw image data from the attached image sensor is fed into the

color pipeline. The user also has the option to select a number of test patterns to be

input instead of sensor data. The test pattern is fed to the IFP for testing the image pipe-

line without sensor operation.

The test patterns can be selected by programming variables. To select enter test pattern

mode, set R0xC88F to 0x02 and issue a Change- Config request; to exit this mode, set

R0xC88F to 0x00.

FRAME_SYNC

TRIGGER_OUT

FV_OUT

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