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ST7MC1 データシート(PDF) 258 Page - STMicroelectronics |
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ST7MC1 データシート(HTML) 258 Page - STMicroelectronics |
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258 / 308 page ![]() ST7MC1/ST7MC2 258/308 CLOCK AND TIMING CHARACTERISTICS (Cont’d) Figure 137. PLL And Clock Detector Signal Start Up Sequence Notes: 1. Lock does not go low without resetting the PLLEN bit. 2. Before setting the CKSEL bit by software in order to switch to the PLL clock, a period of tlock must have elapsed. 3. 2 clock cycles are missing after CKSEL = 1 4. CKSEL bit must be set before enabling the CSS interrupt (CSSIE=1). OSCIN PLLEN PLL CLOCK LOCK fCLK t lock CSSD CSSIE INTERRUPT t setup t hold 16Mhz 6 Mhz fVCO= OSCIN Clock PLL clock 1) CKSEL 2) 3) (PLL and CKD) 4) |
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