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ST7MC1 データシート(PDF) 270 Page - STMicroelectronics

部品番号 ST7MC1
部品情報  8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI
PDF  308 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST7MC1 データシート(HTML) 270 Page - STMicroelectronics

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12.11 COMMUNICATION INTERFACE CHARACTERISTICS
12.11.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for VDD,
fOSC, and TA unless otherwise specified.
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Figure 147. SPI Slave Timing Diagram with CPHA=0 3)
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
4. Depends on fCPU. For example, if fCPU=8MHz, then TCPU = 1/fCPU =125ns and tsu(SS)=550ns
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master
fCPU=8MHz
fCPU/128
0.0625
fCPU/4
2
MHz
Slave
fCPU=8MHz
0
fCPU/2
4
tr(SCK)
tf(SCK)
SPI clock rise and fall time
see I/O port pin description
tsu(SS)
1)
SS setup time 4)
Slave
(4 x TCPU) + 50
ns
th(SS)
1)
SS hold time
Slave
120
tw(SCKH)
tw(SCKL)
SCK high and low time
Master
Slave
100
90
tsu(MI)
tsu(SI)
Data input setup time
Master
Slave
100
100
th(MI)
th(SI)
Data input hold time
Master
Slave
100
100
ta(SO)
Data output access time
Slave
0
120
tdis(SO)
Data output disable time
Slave
240
tv(SO)
Data output valid time
Slave (after enable edge)
120
th(SO)
Data output hold time
0
tv(MO)
Data output valid time
Master (after enable edge)
120
th(MO)
Data output hold time
0
SS INPUT
CPHA=0
MOSI INPUT
MISO OUTPUT
CPHA=0
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
tv(SO)
ta(SO)
tsu(SI)
th(SI)
MSB OUT
MSB IN
BIT6 OUT
LSB IN
LSB OUT
seenote2
CPOL=0
CPOL=1
tsu(SS)
th(SS)
tdis(SO)
th(SO)
see
note 2
BIT1 IN



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