MSP3410D datasheet(16/83 Pages) MICRONAS

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MSP 34x0D

PRELIMINARY DATA SHEET

Micronas

4.7. I2S Bus Interface

By means of this standardized interface, additional

feature

processors

can

connected

the

MSP 34x0D. Two possible formats are supported: The

standard mode (MODE_REG[4]=0) selects the SONY

format, where the I2S_WS signal changes at the word

boundaries. The so-called PHILIPS format, which is

characterized by a change of the I2S_WS signal one

I2S_CL period before the word boundaries, is selected

by setting MODE_REG[4]=1.

The MSP 34x0D normally serves as the master on the

I2S interface. Here, the clock and word strobe lines are

driven

the

MSP 34x0D.

setting

MODE_REG[3]=1, the MSP 34x0D is switched to a

slave mode. Now, these lines are input to the

MSP 34x0D and the master clock is synchronized to

576 times the I2S_WS rate (32 kHz). NICAM operation

is not possible in this mode.

The I2S bus interface consists of five pins:

1. I2S_DA_IN1, I2S_DA_IN2:

For input, four channels (two channels per line,

2*16 bits) per sampling cycle (32 kHz) are transmit-

ted.

2. I2S_DA_OUT:

For output, two channels (2*16 bits) per sampling

cycle (32 kHz) are transmitted.

3. I2S_CL:

Gives the timing for the transmission of I2S serial

data (1.024 MHz).

4. I2S_WS:

The I2S_WS word strobe line defines the left and

right sample.

A precise I2S timing diagram is shown in Fig. 4–6.

Fig. 4–6: I2S bus timing diagram

(Data: MSB first)

R LSB L LSB

16 bit right channel

L LSB

R MSB

Detail C

PHILIPS Mode

SONY Mode

I2S_WS

I2S_CL

I2S_DAIN

Detail A

PHILIPS Mode

SONY Mode

Detail B

PHILIPS/SONY Mode programmable by MODE_REG[4]

R LSB

R LSB L MSB

L MSB

I2S_DAOUT

16 bit right channel

16 bit left channel

FI2SWS

I2S_CL

Detail C

I2S_WS as INPUT

I2S_WS as OUTPUT

1/FI2SCL

TI2SWS1

TI2SWS2

TI2S5

TI2S6

Detail A,B

I2S_CL

I2S_DA_IN

I2S_DA_OUT

TI2S1

TI2S2

TI2S3

TI2S4

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