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Timing and AC Characteristics

BROADCOM

September 9, 2013 • 20730-DS108-R

Page 49

BCM20730 Data Sheet

BROADCOM CONFIDENTIAL

SPI Timing

The SPI interface supports clock speeds up to 12 MHz with VDDIO ≥ 2.2V. The supported clock speed is 6 MHz

when 2.2V ≥ VDDIO ≥ 1.62V.

Figure 13 shows the timing diagram. SPI timing values for different values of SCLK and VDDM are shown in

Table 19, Table 20 on page 50, Table 21 on page 50, Table 22 on page 51.

Figure 13: SPI Timing Diagram

Table 19: SPI1 Timing Values—SCLK = 12 MHz and VDDM = 3.2Va

a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 12 MHz. The

speed can be adjusted to as low as 400 Hz by configuring the firmware.

Reference Characteristics

Symbol

Min

Typicalb

b. Typical timing based on 20 pF/1 MΩ load and SCLK = 12 MHz.

Max

Unit

Output setup time, from MOSI

data valid to sample edge of SCLK

Tds_mo

–

Output hold time, from sample

edge of SCLK to MOSI data update

Tdh_mo

–

Input setup time, from MISO data

valid to sample edge of SCLK

Tds_mi

–

TBD

–

Input hold time, from sample

edge of SCLK to MISO data update

Tdh_mi

–

TBD

–

c. CS timing is firmware controlled.

Time from CS assert to first SCLK

edge

Tsu_cs

½ SCLK period – 1

–

Time from first SCLK edge to CS

deassert

Thd_cs

½ SCLK period

–

MOSI

SCLK

Mode 1

MISO

Invalid bit

MSB

LSB

SCLK

Mode 3

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