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LAN91C111 データシート(PDF) 92 Page - Microchip Technology |
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LAN91C111 データシート(HTML) 92 Page - Microchip Technology |
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92 / 125 page  2011-2016 Microchip Technology Inc. DS00002276A-page 93 LAN91C111 nIOWR nWR I/O Write strobe - asynchronous write access. Address is valid before leading edge. Data is latched on trailing edge. IOCHRDY ARDY This signal is negated on leading nRD, nWR if necessary. It is then asserted on CLK rising edge after the access condition is satisfied. RESET RESET A0 nBE0 nSBHE nBE1 IRQn INTR0 D0-D15 D0-D15 16 bit data bus. The bus byte(s) used to access the device are a function of nBE0 and nBE1: Not used = tri-state on reads, ignored on writes nIOCS16 nLDEV buffered nLDEV is a totem pole output. Must be buffered using an open collector driver. nLDEV is active on valid decodes of A15-A4 and AEN=0. UNUSED PINS GND nADS VCC nBE2, nBE3, nCYCLE, W/nR, nRDYRTN, LCLK No upper word access. TABLE 12-2: HIGH-END ISA OR NON-BURST EISA MACHINES SIGNAL CONNECTORS (CONTINUED) ISA Bus Signal LAN91C111 Signal Notes nBE0 nBE1 D0-D7 D8-D15 0 0 Lower Upper 0 1 Lower Not used 1 0 Not used Upper |
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