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LAN89730 データシート(PDF) 23 Page - Microchip Technology

部品番号 LAN89730
部品情報  Implements Reduced Power Operating Modes
PDF  218 Pages
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メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN89730 データシート(HTML) 23 Page - Microchip Technology

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 2013-2015 Microchip Technology Inc.
DS60001348A-page 23
LAN89730
TABLE 2-7:
POWER PINS AND GROUND PAD
Num Pins
Name
Symbol
Buffer
Type
Description
5
+3.3 V I/O
Power
VDD33IO
P
Refer to Chapter 3.0, "Power Connections" and
the device reference schematics for connection
information.
3
+3.3 V Ana-
log Power
VDD33A
P
Refer to Chapter 3.0, "Power Connections" and
the device reference schematics for connection
information.
2
+1.2 V Digital
Core Power
VDD12CORE
P
Refer to Chapter 3.0, "Power Connections" and
the device reference schematics for connection
information.
1
+1.2 V USB
PLL Power
VDD12USBPLL
P
This pin must be connected to VDD12CORE for
proper operation.
Refer to Chapter 3.0, "Power Connections" and
the device reference schematics for additional
connection information.
1
+1.2 V HSIC
Power
VDD12A
P
This pin must be connected to VDD12CORE for
proper operation.
Refer to Chapter 3.0, "Power Connections" and
the device reference schematics for connection
information.
1
+1.2 V Ether-
net PLL
Power
VDD12PLL
P
This pin must be connected to VDD12CORE for
proper operation.
Refer to Chapter 3.0, "Power Connections" and
the device reference schematics for additional
connection information.
Exposed
pad on
package
bottom
Ground
VSS
P
Common Ground
TABLE 2-8:
NO-CONNECT PINS
Num Pins
Name
Symbol
Buffer
Type
Description
1
No Connect
NC
-
This pin must be left floating for normal device
operation.



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