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CY7C63000A/CY7C63001A
CY7C63100A/CY7C63101A
FOR
FOR
Document #: 38-08026 Rev. **
Page 5 of 31
8-bit
Timer
PinConfigurations (Top View)
Logic Block Diagram
USB
D+,D–
PORT
P0.0–P0.7
Interrupt
Controller
0
PORT
P1.0–P1.7
1
8-bit
RISC
OSC
RAM
128-Byte
EPROM
2/4 KByte
1
2
3
4
5
6
7
9
13
14
15
16
17
18
20
19
P0.0
P0.1
P0.2
P0.3
P1.0
P1.2
VSS
CEXT
P0.4
P1.1
P0.6
P0.7
D+
P1.3
D–
VCC
DIP/SOIC
12
P0.5
8
VPP
XTALIN
XTALOUT
10
11
core
Power-
on Reset
Engine
Watch
Timer
Dog
6-MHz
CERAMIC RESONATOR
1
2
3
4
5
6
9
11
15
16
17
18
19
20
22
21
P0.0
P0.1
P0.2
P0.3
P1.0
P1.2
VSS
CEXT
P0.6
P1.5
P1.1
P1.3
D+
P1.7
D–
VCC
24-pin
14
P0.7
10
VPP
XTALIN
XTALOUT
12
13
7
8
P1.4
P1.6
24
23
P0.4
P0.5
INSTANT-ON
NOW™
R/CEXT
VCC/VSS
SOIC/QSOP
20-pin