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CY7C63000A/CY7C63001A
CY7C63100A/CY7C63101A
FOR
FOR
Document #: 38-08026 Rev. **
Page 6 of 31
3.0
Pin Definitions
Name
I/O
20-Pin
24-pin
Description
P0.0
I/O
1
1
Port 0 bit 0
P0.1
I/O
2
2
Port 0 bit 1
P0.2
I/O
3
3
Port 0 bit 2
P0.3
I/O
4
4
Port 0 bit 3
P0.4
I/O
20
24
Port 0 bit 4
P0.5
I/O
19
23
Port 0 bit 5
P0.6
I/O
18
22
Port 0 bit 6
P0.7
I/O
17
21
Port 0 bit 7
P1.0
I/O
5
5
Port 1 bit 0
P1.1
I/O
16
20
Port 1 bit 1
P1.2
I/O
6
6
Port 1 bit 2
P1.3
I/O
15
19
Port 1 bit 3
P1.4
I/O
–
7
Port 1 bit 4
P1.5
I/O
–
18
Port 1 bit 5
P1.6
I/O
–
8
Port 1 bit 6
P1.7
I/O
–
17
Port 1 bit 7
XTALIN
I
10
12
Ceramic resonator in
XTALOUT
O
11
13
Ceramic resonator out
CEXT
I/O
9
11
Connects to external R/C timing circuit for optional ‘suspend’ wakeup
D+
I/O
14
16
USB data+
D–
I/O
13
15
USB data–
VPP
–
8
10
Programming voltage supply, tie to ground during normal operation
VCC
–
12
14
Voltage supply
VSS
–
7
9
Ground
4.0
Pin Description
Name
Description
VCC
1 pin. Connects to the USB power source or to a nominal 5V power supply. Actual VCC range can vary
between 4.0V and 5.25V.
VSS
1 pin. Connects to ground.
VPP
1 pin. Used in programming the on-chip EPROM. This pin should be tied to ground during normal operations.
XTALIN
1 pin. Input from an external ceramic resonator.
XTALOUT
1 pin. Return path for the ceramic resonator (leave unconnected if driving XTALIN from an external oscilla-
tor).
P0.0–P0.7,
P1.0–P1.7
16 pins. P0.0–P0.7 are the 8 I/O lines in Port 0. P1.0–P1.7 are the 8 I/O lines in Port 1. P1.0–P1.3 are
supported in the CY7C6300XA. All I/O pins include bit-programmable pull-up resistors. However, the sink
current of each pin can be programmed to one of sixteen levels. Besides functioning as GPIO lines, each
pin can be programmed as an interrupt input. The interrupt is edge-triggered, with programmable polarity.
D+, D–
2 pins. Bidirectional USB data lines. An external pull-up resistor must be connected between the D pin and
VCC to select low-speed USB operation.
CEXT
1 pin. Open-drain output with Schmitt trigger input. The input is connected to a rising edge-triggered interrupt.
CEXT may be connected to an external RC to generate a wake-up from Suspend mode. See Section 5.4.
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