MB39C015 datasheet(13/43 Pages) CYPRESS

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MB39C015

Document Number: 002-08364 Rev. *A

Page 13 of 43

(Continued)

(Ta

 25 °C , AVDD  DVDD1  DVDD2  3.7 V, VOUT1/VOUT2 setting value  2.5 V, MODE1/MODE2  0 V)

*1 : The minimum value of AVDD = DVDD1 = DVDD2 is the 2.5 V or VOUT setting value + 0.6 V, whichever is higher.

*2 : The + leak at the LX1 pin and LX2 pin includes the current of the internal circuit.

*3 : Sum of the current flowing into the AVDD, the DVDD1, and the DVDD2 pins.

*4 : Current consumption based on 100% ON-duty (High side FET in full ON state). The SW FET gate drive current is not included

because the device is in full ON state (no switching operation). Also the load current is not included

Parameter

Symbol

Pin No.

Condition

Value

Unit

Min

Typ

Max

Control block

CTL threshold

voltage

VTHHCT

1, 2, 3

–

0.55

0.95

1.45

VTHLCT

–

0.40

0.80

1.30

CTL pin

input current

IICTL

0 V

 CTLP/CTL1/CTL2 

3.7 V

–

1.0

A

Reference

voltage block

VREF voltage

VREF

6VREF

 0 mA

1.274

1.300

1.326

VREF Load

stability

LOADREF

VREF

 1.0 mA

–

General

Shut down

power supply

current

IVDD1

5, 11,

12, 19,

CTLP/CTL1/CTL2

 0 V

State of all circuits OFF*3

–

1.0

A

IVDD1H

CTLP/CTL1/CTL2

 0 V,

VDD

 5.5 V

State of all circuits OFF*3

–

1.0

A

Power supply current

(DC/DC mode)

IVDD31

1. CTLP

 0 V, CTL1  3.7 V,

CTL2

 0 V

2. CTLP

 0 V, CTL1  0 V,

CTL2

 3.7 V

OUT

 0 A

–

3.5

IVDD32

CTLP

 0 V, CTL1/CTL2 

3.7 V, OUT

 0 A

–

7.0

20.0

Power supply current

(voltage detection

mode)

IVDD5

CTLP

 3.7 V,

CTL1/CTL2

 0 V,

–

A

Power-on

invalid current

IVDD

1. CTL1

 3.7 V, CTL2  0 V

2. CTL1

 0 V, CTL2  3.7 V

VOUT1/VOUT2

 90%

OUT

 0 A*4

–

1000

2000

A

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