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CS5540-AS データシート(PDF) 12 Page - Cirrus Logic |
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CS5540-AS データシート(HTML) 12 Page - Cirrus Logic |
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12 / 22 page ![]() CS5540 12 DS503PP1 2.3 Power Supply Arrangements The CS5540 is designed to operate with a total sup- ply voltage of 3.0 V ± 5%. For maximum flexibili- ty, separate pins are provided for VA+, VA-, VD+, and DGND, which is especially useful with ground-referenced input signals. Figure 7 illustrates the CS5540 connected with a single +3.0 V supply for both the analog and digital sections. 2.4 Clock Generator The CS5540 includes an oscillator circuit which can be connected with an external crystal to pro- vide the master clock for the chip. The chip is de- signed to operate using a low-cost 32.768 kHz “tuning fork” type crystal. One lead of the crystal should be connected to OSC1 and the other to OSC2. A 10 megohm resistor is required in parallel with the crystal. Lead lengths should be minimized to reduce stray capacitance. Note that the converter will operate with an external (CMOS compatible) clock with frequencies up to 40kHz, applied to the OSC1 pin. 2.5 Serial Port Interface The CS5540’s serial interface consists of three con- trol lines: CS, SDO, and SCLK. CS, Chip Select, is the control line which enables access to the serial port. If the CS pin is tied to logic 0, the port can function as a three wire interface. SDO, Serial Data Out, is the data signal used to transfer output data from the converters. The SDO output will be held at high impedance any time CS is at logic 1. SCLK, Serial Clock, is the serial bit-clock which controls the shifting of data to or from the ADC’s serial port. The CS pin must be held at logic 0 be- fore SCLK transitions can be recognized by the port logic. To accommodate opto-isolators, SCLK is designed with a Schmitt-trigger input. 2.6 Input Channel Selector CHS, the Channel Select input, permits the user to select between AIN1 and AIN2 for data conver- sions. When CHS = 0, AIN1 is converted. When CHS = 1, AIN2 is converted. Note that since the converter continuously converts the input selected Figure 7. CS5540 Configured with a single +3.0 V Supply OSC2 VD+ VA+ VREF+ VREF- DGND AIN1+ SCLK SDO CS5540 OSC1 CS +3.0 V Analog 16 15 3 2 11 9 8 6 10 5 12 Optional Clock Source Serial Data Interface 5 kHz ~ 40 kHz AIN1- 4 VA- 1 0.1 µF 0.1 µF 10 Ω AIN2+ AIN2- + - Voltage Reference 14 13 CHS 7 Supply Analog Signal Sources Channel Selection 10 M Ω |
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