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SLB128B データシート(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部品番号 SLB128B
部品情報  Transmitter with built-in scaler for LVDS Display Interface (LDI)
PDF  48 Pages
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メーカー  NSC [National Semiconductor (TI)]
ホームページ  http://www.national.com
Logo NSC - National Semiconductor (TI)

SLB128B データシート(HTML) 6 Page - National Semiconductor (TI)

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AC Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Units
LLHT
LVDS Low-to-High Transition Time (Figure 3). (Note 7)
0.14
0.8
ns
LHLT
LVDS High-to-Low Transition Time (Figure 3). (Note 7)
0.11
0.8
ns
TBIT
Transmitter Output Bit Width
DUAL pin = V
CC or
Gnd
1/7 TCIP
ns
DUAL pin = 1⁄2V
CC
2/7 TCIP
ns
TCCS
TxOUT Channel to Channel Skew
100
ps
TPPOS0
Transmitter Output Pulse Position for Bit 0
(previous cycle) from CLK1P rising edge
(Note 7).
f = 65 MHz, DUAL pin
=V
CC
−0.49
0
+0.49
ns
TPPOS1
Transmitter Output Pulse Position for Bit1
(previous cycle) from CLK1P rising edge.
(Note 7)
f = 65 MHz, DUAL pin
=V
CC
(1/7)TCIP
−0.49
(1/7)TCIP
(1/7)TCIP
+0.49
ns
TPPOS2
Transmitter Output Pulse Position for Bit2
from CLK1P rising edge. (Note 7)
f = 65 MHz, DUAL pin
=V
CC
(2/7)TCIP
−0.49
(2/7)TCIP
(2/7)TCIP
+0.49
ns
TPPOS3
Transmitter Output Pulse Position for Bit3
from CLK1P rising edge. (Note 7)
f = 65 MHz, DUAL pin
=V
CC
(3/7)TCIP
−0.49
(3/7)TCIP
(3/7)TCIP
+0.49
ns
TPPOS4
Transmitter Output Pulse Position for Bit4
from CLK1P rising edge. (Note 7)
f = 65 MHz, DUAL pin
=V
CC
(4/7)TCIP
−0.49
(4/7)TCIP
(4/7)TCIP
+0.49
ns
TPPOS5
Transmitter Output Pulse Position for Bit5
from CLK1P rising edge. (Note 7)
f = 65 MHz, DUAL pin
=V
CC
(5/7)TCIP
−0.49
(5/7)TCIP
(5/7)TCIP
+0.49
ns
TPPOS6
Transmitter Output Pulse Position for Bit6
from CLK1P rising edge. (Note 7)
f = 65 MHz, DUAL pin
=V
CC
(6/7)TCIP
−0.49
(6/7)TCIP
(6/7)TCIP
+0.49
ns
TSTC
DxIN Setup to CLKINP (Figure 6) (Note 7)
0.8
ns
THTC
DxIN Hold to CLKINP (Figure 6) (Note 7)
0.8
ns
TJCC
Transmitter Jitter Cycle-to-cycle (Note 4)
f = 85 MHz, DUAL pin
= Gnd
114
ps
f = 54 MHz, DUAL pin
=V
CC
114
ps
TPLLS
Transmitter Phase Lock Loop Set (Figure 7) (Note 7)
10
ms
TPDD
Transmitter Powerdown Delay (Figure 8) (Note 7)
100
ns
Transmitter Input to Output Latency for
single in-to-dual out mode. Figure 9
f = 170 MHz (Note 6)
1.5 TCIP
+4.1
ns
www.national.com
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