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AD4001 データシート(PDF) 21 Page - Analog Devices |
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AD4001 データシート(HTML) 21 Page - Analog Devices |
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21 / 34 page ![]() AD4001 Data Sheet Rev. 0 | Page 20 of 33 High-Z Mode The AD4001 incorporates high-Z mode, which reduces the nonlinear charge kickback when the capacitor DAC switches back to the input at the start of acquisition. Figure 40 shows the input current of the AD4001 with high-Z mode enabled and disabled. The low input current makes the ADC easier to drive than the traditional SAR ADCs available in the market, even with high-Z mode disabled. The input current reduces further to sub microampere range when high-Z mode is enabled. The high-Z mode is disabled by default but can be enabled by writing to the register (see Table 14). Disable high-Z mode for input frequencies above 100 kHz or multiplexing. 15 6 –12 –6 12 0 3 –9 9 –3 –15 –5 3 1 –1 –3 5 2 0 –2 –4 4 INPUT DIFFERENTIAL VOLTAGE (V) 25°C HIGH-Z ENABLED 25°C HIGH-Z DISABLED Figure 40. Input Current vs. Input Differential Voltage, VIO = 3.3 V, VREF = 5 V System designers looking to achieve the optimum data sheet performance from high resolution precision SAR ADCs are often forced to use a dedicated high power, high speed amplifier to drive the traditional switched capacitor SAR ADC inputs for their precision applications, which is one of the common pain points encountered in designing a precision data acquisition signal chain. The benefits of high-Z mode are low input current for slow (<10 kHz) or dc type signals and improved distortion (THD) performance over a frequency range of up to 100 kHz. High-Z mode allows a choice of lower power and bandwidth precision amplifiers with a lower RC filter cutoff to drive the ADC, removing the need for dedicated high speed ADC drivers, which saves system power, size, and cost in precision, low bandwidth applications. High-Z mode allows the amplifier and RC filter in front of the ADC to be chosen based on the signal bandwidth of interest and not based on the settling requirements of the switched capacitor SAR ADC inputs. Additionally, the AD4001 can be driven with a much higher source impedance than traditional SARs, which means the resistor in the RC filter can have a value 10 times larger than previous SAR designs and, with high-Z mode enabled, can tolerate even larger impedance. Figure 41 shows the THD performance for various source impedances with high-Z mode disabled and enabled. –125 –120 –115 –110 –105 –100 –95 –90 –85 –80 110 20 INPUT FREQUENCY (kHz) 150Ω HIGH-Z DISABLED 150Ω HIGH-Z ENABLED 510Ω HIGH-Z DISABLED 510Ω HIGH-Z ENABLED 1kΩ HIGH-Z DISABLED 1kΩ HIGH-Z ENABLED Figure 41. THD vs. Input Frequency for Various Source Impedance, VREF = 5 V Figure 42 and Figure 43 show the AD4001 SNR and THD performance using the ADA4077-1 (IQUIESCENT = 400 μA/amplifier) and ADA4610-1 (IQUIESCENT = 1.5 mA/amplifier) precision amplifiers when driving the AD4001 at the full throughput of 2 MSPS for high-Z mode enabled and disabled with various RC filter values. These amplifiers achieve 93 dB to 96 dB typical SNR and better than −110 dB THD with high-Z mode enabled. THD is approximately 10 dB better with high-Z mode enabled, even for large R values. SNR holds up close to 96dB, even with a very low RC bandwidth cutoff. When high-Z mode is enabled, the ADC consumes approximately 2 mW/MSPS extra power; however, this power is still significantly lower than using dedicated ADC drivers like the ADA4807-1. For any system, the front end usually limits the overall ac/dc performance of the signal chain. It is evident from the data sheets of the selected precision amplifiers, shown in Figure 42 and Figure 43, that their own noise and distortion performance dominates the SNR and THD specification at a certain input frequency. 260kHz 1.3kΩ 470pF 498kHz 680Ω 470pF 1.3MHz 680Ω 180pF 2.27MHz 390Ω 180pF 4.42MHz 200Ω 180pF RC FILTER BANDWIDTHS (Hz), RESISTOR (Ω), CAPACITOR (pF) 73 76 79 82 85 88 91 94 97 ADA4077-1 HIGH-Z DISABLED ADA4077-1 HIGH-Z ENABLED ADA4610-1 HIGH-Z DISABLED ADA4610-1 HIGH-Z ENABLED Figure 42. SNR vs. RC Filter Bandwidth for Various Precision ADC Drivers, VREF = 5 V, fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled), VIO = 3.3 V |
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