PC87311A datasheet(19/78 Pages) NSC

19 / 78 page

30 FDC Register Description (Continued)

311 SRAPS2 Mode

DESC

IRQ6

DRV2

STEP

TRK0

HDSEL

INDX

DIR

PEND

RESET

COND

Interrupt Pending

This active high bit reflects the

state of the IRQ6 pin

2nd Drive Installed

Active low status of the

DRV2 disk interface input indicating if a second

drive has been installed

Step

Active high status of the STEP disk interface

output

Track 0

Active low status of the TRK0 disk inter-

face input

Head Select

Active high status of the HDSEL disk

interface output

Index

Active low status of the INDEX disk interface

input

Write Protect

Active low status of the WP disk in-

terface input

Direction

Active high status of the DIR disk inter-

face output

312 SRA

Model 30 Mode

DESC

IRQ6

DRQ

STEP

TRK0

HDSEL

INDX

DIR

PEND

RESET

COND

Interrupt Pending

This active high bit reflects that

state of the IRQ6 pin

DMA Request

Active high status of the DRQ signal

Step

Active high status of the latched STEP disk

interface output This bit is latched with the STEP

output going active and is cleared with a read from

the DIR or with a hardware or software reset

Track 0

Active high status of TRK0 disk interface

input

Head Select

Active low status of the HDSEL disk

interface output

Index

Active high status of the INDEX disk inter-

face input

Write Protect

Active high status of the WP disk

interface input

Direction

Active low status of the DIR disk inter-

face output

32 STATUS REGISTER B (SRB)

Read Only

This is a read-only diagnostic register that is part of the

PS2 floppy controller register set and is enabled when in

the PS2 or Model 30 mode The SRB can be read at any

time when in PS2 mode In the PC-AT mode D7 – D0 are

TRI-STATE during a mP read

321 SRBPS2 Mode

DESC

DR0

WDATA

RDATA

WGATE

MTR1

MTR0

RESET

COND

Reserved

Always 1

Reserved

Always 1

Drive Select 0

Reflects the status of the Drive Se-

lect 0 bit in the DOR (address 2 bit 0) This bit is

cleared after a hardware reset not a software reset

Write Data

Every inactive edge transition of the

WDATA disk interface output causes this bit to

change states

Read Data

Every inactive edge transition of the

RDATA disk interface output causes this bit to

change states

Write Gate

Active high status of the WGATE disk

interface output

Motor Enable 1

Active high status of the MTR1

disk interface output Low after a hardware reset

unaffected by a software reset

Motor Enable 0

Active high status of the MTR0

disk interface output Low after a hardware reset

unaffected by a software reset

322 SRBModel 30 Mode

DESC

DRV2

DR1

DR0

WDATA

RDATA

WGATE

DR3

DR2

RESET

COND

2nd Drive Installed

Active low status of the

DRV2 disk interface input

Drive Select 1

Active low status of the DR1 disk

interface output

Drive Select 0

Active low status of the DR0 disk

interface output

Write Data

Active high status of latched WDATA

signal This bit is latched by the inactive going edge

of WDATA and is cleared by a read from the DIR

This bit is not gated by WGATE

PC87311A データシート(PDF) 19 Page - National Semiconductor (TI)

PC87311A データシート(HTML) 19 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

データシートダウンロード

リンク URL

PC87311A データシート(PDF) 19 Page - National Semiconductor (TI)

PC87311A データシート(HTML) 19 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

データシート ダウンロード

リンク URL

データシートダウンロード