STCF05

I²C bus interface

Doc ID 15257 Rev 4

17/33

8.5

Interface protocol

The interface protocol is composed of (Figure 5):

- A start condition (START)

- A Device address + R/W bit (read =1 / write =0)

- A Register address byte

- A sequence of data n* (1 byte + acknowledge)

- A stop condition (STOP)

The register address byte determines the first register in which the read or write operation

takes place. When the read or write operation is finished, the register address is

automatically incremented.

8.6

Writing to a single register

Writing to a single register starts with a START bit followed by the 7 bit device address of

operation. Then the master waits for an acknowledge from STCF05. Then the 8 bit address

of register is sent to STCF05. It is also followed by an acknowledge pulse. The last

transmitted byte is the data that is going to be written to the register. It is again followed by

an acknowledge pulse from STCF05. The master then generates a STOP bit and the

communication is over. See Figure 8 below.

Figure 7.

Acknowledge on I²C bus

Table 8.

Interface protocol

Device address + R/W bit

Register address

Data

765

4

3

2

1

0

7

6

5

4

3210

765

4

321

0

S

T

A

R

T

M

S

B

L

S

B

R

W

A

C

K

M

S

B

L

S

B

A

C

K

M

S

B

L

S

B

A

C

K

S

T

O

P