STCF05

I²C bus interface

Doc ID 15257 Rev 4

19/33

acknowledge pulse and starts to send the data to the master. No acknowledge pulse from

the master is required after receiving the data. Then the master generates a STOP bit to

terminate the communication. See Figure 10.

8.9

Reading from multiple registers with incremental addressing

Reading from multiple registers starts in the same way like reading from a single register. As

soon as the first register is read, the register address is automatically incremented. If the

master generates an acknowledge pulse after receiving the data from the first register, then

reading of the next register can start immediately without sending the device address and

the register address again. The last acknowledge pulse before the STOP bit is not required.

See Figure 11.

Figure 10.

Reading from a single register

S

T

A

R

T

DEVICE

ADDRESS

7 bits

A

C

K

W

R

I

T

E

M

S

B

L

S

B

R

/

W

ADDRESS

OF

REGISTER

A

C

K

M

S

B

L

S

B

S

T

A

R

T

A

C

K

R

/

W

R

E

A

D

DEVICE

ADDRESS

7 bits

DATA

L

S

B

S

T

O

P

N

O

A

C

K

SDA LINE

S

T

A

R

T

DEVICE

ADDRESS

7 bits

A

C

K

W

R

I

T

E

M

S

B

L

S

B

R

/

W

ADDRESS

OF

REGISTER

A

C

K

M

S

B

L

S

B

S

T

A

R

T

A

C

K

R

/

W

R

E

A

D

DEVICE

ADDRESS

7 bits

DATA

L

S

B

S

T

O

P

N

O

A

C

K

SDA LINE

Figure 11.

Reading from multiple registers

S

T

A

R

T

DEVICE

ADDRESS

7 bits

A

C

K

W

R

I

T

E

M

S

B

L

S

B

R

/

W

ADDRESS OF

REGISTER i

A

C

K

M

S

B

L

S

B

S

T

A

R

T

A

C

K

R

/

W

R

E

A

D

DEVICE

ADDRESS

7 bits

DATA i

A

C

K

S

T

O

P

L

S

B

DATA i+1

A

C

K

L

S

B

DATA i+2

A

C

K

L

S

B

DATA i+2

L

S

B

DATA i+n

M

S

B

M

S

B

M

S

B

M

S

B

A

C

K

L

S

B

N

O

A

C

K

SDA LINE

S

T

A

R

T

DEVICE

ADDRESS

7 bits

A

C

K

W

R

I

T

E

M

S

B

L

S

B

R

/

W

ADDRESS OF

REGISTER i

A

C

K

M

S

B

L

S

B

S

T

A

R

T

A

C

K

R

/

W

R

E

A

D

DEVICE

ADDRESS

7 bits

DATA i

A

C

K

S

T

O

P

L

S

B

DATA i+1

A

C

K

L

S

B

DATA i+2

A

C

K

L

S

B

DATA i+2

L

S

B

DATA i+n

M

S

B

M

S

B

M

S

B

M

S

B

A

C

K

L

S

B

N

O

A

C

K

SDA LINE