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TNETV2501INPGF データシート(PDF) 55 Page - Texas Instruments |
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TNETV2501INPGF データシート(HTML) 55 Page - Texas Instruments |
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55 / 197 page  Functional Overview 55 December 2002 − Revised November 2008 SPRS206K 8 Receiver Buffer Register Divisor Latch (LS) Divisor Latch (MS) Baud Generator Receiver FIFO Line Status Register Transmitter Holding Register Modem Control Register Line Control Register Transmitter FIFO Interrupt Enable Register Interrupt Identification Register FIFO Control Register Interrupt/ Event Control Logic S e l e c t Data Bus Buffer RX TX Peripheral Bus S e l e c t Receiver Shift Register Receiver Timing and Control Transmitter Timing and Control Transmitter Shift Register Control Logic 16 8 8 8 8 8 Interrupt to CPU 16 8 pin pin 8 8 8 8 Power and Emulation Control Register Event to DMA controller Figure 3−9. UART Functional Block Diagram |
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