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L6751C データシート(PDF) 23 Page - STMicroelectronics

部品番号 L6751C
部品情報  Digitally controlled dual PWM for Intel VR12 and AMD SVI
PDF  57 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L6751C データシート(HTML) 23 Page - STMicroelectronics

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L6751C
Device configuration and pin-strapping tables
57
.
10
220
0000b
(VR12)
C0h / 80h
ON
ON
10
Open
OFF
1. Recommended values, divider needs to be connected between VCC5 pin and GND.
2. In DDR mode, when enabled, droop has 1/4th scaling factor.
3. SVI address for multi-phase. Single-phase is further offset by 0001b. In AMD mode, SVI address defaults according to
AMD specifications.
4. PMBus address for multi-phase (read/write). Single-phase is further offset by 02h. When in VR12 CPU mode,
RCOMP = 12.5 k
 to GND, select between Cxh (Open) and 8xh (if installed) PMBus address.
Table 9. ADDR pin-strapping(1), (2) (continued)
Rdown [k
]Rup [k]
ADDR
ADDR (3)
PMBADDR(4)
JMode
DROOP multi-
phase
DROOP single-
phase
Table 10. BOOT / TMAX pin-strapping(1), (2)
Rdown
[k
]
Rup
[k
]
BOOT - Intel address 0000b(3)
Intel address 0010b, 0100b (3)
TMAX [C]
Multi-
phase
Single-
phase
Link rest
JMode
VBOOT
Link rest
10
1.5
1.000 V
0.000 V
VSA
32
sec
(debug)
ON
1.500 V
32
sec
(debug)
130
10
2.7
120
22
6.8
110
10
3.6
100
27
11
1.000 V
1.000 V
VSA
32
sec
(debug)
10
sec
(functional)
130
12
5.6
120
82
43
110
13
7.5
100
56
36
0.000 V
1.100 V
VSA
10
sec
(functional)
ON
1.350 V
32
sec
(debug)
130
18
13
120
15
12
110
18
16
100
15
14.7
0.000 V
1.000 V
VSA
10
sec
(functional)
10
sec
(functional)
130
10
11
120
18
22
110
56
75
100



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