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ST72344S2 データシート(PDF) 69 Page - STMicroelectronics |
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ST72344S2 データシート(HTML) 69 Page - STMicroelectronics |
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69 / 247 page  ST72344xx, ST2345xx Power-saving modes Doc ID 12321 Rev 6 69/247 Note: As soon as active halt is enabled, executing a HALT instruction while the Watchdog is active does not generate a reset. This means that the device cannot spend more than a defined delay in this power saving mode. Figure 30. Active-halt timing overview Figure 31. Active-halt mode flowchart Note: 1 This delay occurs only if the MCU exits Active-Halt mode by means of a reset. 2 Peripheral clocked with an external clock source can still be active. 3 Only the RTC interrupt and some specific interrupts can exit the MCU from Active-halt mode (such as external interrupt). Refer to Table 17 for more details. 4 Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits in the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped. halt Run Run 256 OR 4096 cycle delay (after reset) Reset or interrupt HALT instruction Fetch vector Active- (Active-halt enabled) HALT INSTRUCTION RESET INTERRUPT 3) Y N N Y CPU OSCILLATOR PERIPHERALS 2) I[1:0] BITS ON OFF 10 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON OFF XX 4) ON CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON ON XX 4) ON 256 OR 4096 CPU CLOCK CYCLE DELAY (MCCSR.OIE=1) (AWUCSR.AWUEN=0) |
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