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STM8S003F3 データシート(PDF) 76 Page - STMicroelectronics |
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STM8S003F3 データシート(HTML) 76 Page - STMicroelectronics |
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76 / 104 page  Electrical characteristics STM8S003F3 STM8S003K3 76/104 DocID018576 Rev 9 Figure 35. Typical NRST pull-up resistance vs VDD @ 4 temperatures Figure 36. Typical NRST pull-up current vs VDD @ 4 temperatures The reset network shown in Figure 37 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 38. Otherwise the reset is not taken into account internally. For power consumption sensitive applications, the capacity of the external reset capacitor can be reduced to limit charge/discharge current. If the NRST signal is used to reset the external circuitry, care must be taken of the charge/discharge time of the external capacitor to fulfill the external device’s reset timing conditions. The minimum recommended capacity is 10 nF. |
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