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STM8TL53x4 データシート(PDF) 62 Page - STMicroelectronics

部品番号 STM8TL53x4
部品情報  Operating conditions
PDF  84 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM8TL53x4 データシート(HTML) 62 Page - STMicroelectronics

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Electrical parameters
STM8TL52x4 STM8TL53x4
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DocID022344 Rev 7
NRST pin
The NRST pin input driver is CMOS. A permanent pull-up is present which is the same as
RPU (see Table 31 on page 56).
Subject to general operating conditions for VDD and TA unless otherwise specified.
The reset network shown in Figure 26 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the VIL max. level specified in
Table 33
. Otherwise the reset is not taken into account internally.
Figure 25. Typical NRST pull-up resistance RPU vs. VDD
Table 33. NRST pin characteristics
Symbol
Parameter
Conditions
Min.
Typ.(1)
1. Data based on characterization results, not tested in production.
Max.
Unit
VIL(NRST) NRST input low level voltage(1)
-VSS
-0.8
V
VIH(NRST) NRST input high level voltage(1)
-1.4
-
VDD
VOL(NRST) NRST output low level voltage
IOL = 2 mA
-
-
VDD-
0.8
RPU(NRST) NRST pull-up equivalent resistor(2)
2. The RPU pull-up equivalent resistor is based on a resistive transistor.
-30
45
60
k
VF(NRST)
NRST input filtered pulse(3)
3. Data guaranteed by design, not tested in production.
--
-
50
ns
tOP(NRST) NRST output pulse width
-
20
-
-
VNF(NRST) NRST input not filtered pulse(3)
-300
-
-



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