STM32L471VG datasheet(36/218 Pages) STMICROELECTRONICS

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Functional overview

STM32L471xx

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DocID027226 Rev 1

3.14

Interrupts and events

3.14.1

Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,

and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-

M4.

The NVIC benefits are the following:

•

Closely coupled NVIC gives low latency interrupt processing

•

Interrupt entry vector table address passed directly to the core

•

Allows early processing of interrupts

•

Processing of late arriving higher priority interrupts

•

Support for tail chaining

•

Processor state automatically saved

•

Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal

interrupt latency.

3.14.2

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 36 edge detector lines used to generate

interrupt/event requests and wake-up the system from Stop mode. Each external line can be

independently configured to select the trigger event (rising edge, falling edge, both) and can

be masked independently A pending register maintains the status of the interrupt requests.

The internal lines are connected to peripherals with wakeup from Stop mode capability. The

EXTI can detect an external line with a pulse width shorter than the internal clock period. Up

to 114 GPIOs can be connected to the 16 external interrupt lines.

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