REV. 0

AD1833A

–13–

MCLK Select

The AD1833A allows the matching of available external MCLK

frequencies to the required internal MCLK rate. The MCLK

modification factor can be selected from 2, 1, or

Bit 4 and Bit 3 of Control Register 3. Internally, the AD1833A

requires an MCLK of 24.576 MHz for sample rates of 48 kHz,

96 kHz, and 192 kHz. In the case of 48 kHz data with an

MCLK of 256

MCLK of 768

followed by a clock doubler. With an MCLK of 512

MCLK is passed through unmodified (see Table XII).

Table XII. MCLK Settings

Bit 4

Bit 3

Modification Factor

00

MCLK

2 Internally

01

MCLK

1 Internally

10

MCLK

11

Reserved

Channel Zero Status

The AD1833A provides individual logic output status indicators

when zero data is sent to a channel for 1024 or more consecutive

sample periods in all modes except right-justified. There is also

Table XIV. MCLK vs. Sample Rate Selection

Sampling Rate

Interpolator Mode

Internal MCLK

Suitable External MCLK Frequencies (MHz)

Required

Required (MHz)

MCLK

2

MCLK

1

MCLK

3

32

8

64

4

16.384

8192

16.384

24.576

128

2

44.1

8

88.2

4

22.5792

11.2896

22.5792

33.8688

176.4

2

48

8

96

4

24.576

12.288

24.576

36.864

192

2

Table XV. Volume Control Registers

Address

Reserved

*

Volume Control

15–12

11

10

9–0

00

10

00

Channel 1 Volume Control (OUTL1)

00

11

Channel 2 Volume Control (OUTR1)

01

00

Channel 3 Volume Control (OUTL2)

01

01

Channel 4 Volume Control (OUTR2)

01

10

Channel 5 Volume Control (OUTL3)

01

11

Channel 6 Volume Control (OUTR3)

*Must be programmed to zero.

a global zero flag that indicates all channels contain zero data.

The polarity of the zero signal is programmable by writing to

Control Bit 2 (see Table XIII). In right-justified mode, the six

individual channel flags are best used as three stereo zero flags

by combining pairs of them through suitable logic gates. Then,

when both the left and right inputs are zero for 1024 clock cycles,

i.e., a stereo zero input for 1024 sample periods, the combined

result of the two individual flags will become active, indicat-

ing a stereo zero.

Table XIII. Zero Detect

Bit 2

Channel Zero Status

0Active High

1Active Low

DAC Volume Control Registers

The AD1833A has six volume control registers, one for each of

the six DAC channels. Volume control is exercised by writing to

the relevant register associated with each DAC. This setting is

used to attenuate the DAC output. Full-scale setting (all 1s) is

equivalent to zero attenuation (see Table XV).