STSAM9708 datasheet(11/30 Pages) ATMEL

11 / 30 page

ATSAM9708

1772D–DRMSD–01/04

Timing Diagrams

All timing conditions: V

CC = 5V, VC3 = 3.3V, tA = 25°C; signals PC_READY, I/O CS16,

D0 - D15 with 220 ohms pull-up, 30 pF capacitance; signal PC_IRQ with 470 ohms pull-

down, 30 pF capacitance; all other outputs except X2 and LFT load capacitance = 30

pF. All timings refer to t

CK, which is the internal master clock period. The internal master

clock frequency is 4 times the frequency at pin X1; therefore, t

CK = tXTAL/4. The sampling

rate is given by 1/(t

CK * 1024). The maximum crystal frequency/clock frequency at X1 is

12.288 MHz (48 kHz sampling rate).

PC Host Interface

Figure 3. Host Interface Read Cycle

Note:

PC_D[15:8] valid only if PC_A[2:1] = 10.

Figure 4. Host Interface Write Cycle

Note:

PC_D[15:8] valid only if PC_A[2:1] = 10.

PC_A[2:0]

PC_CS

PC_RD

PC_ READY

PC_IO16

PC_D[15:0]

tAVCS

tCSLRDL

tPRD

tRDHCSB

tRDLIORL

tPIOR

tCSLIOCS

tIORHDV

tCSHIOCS

tRDLDV

tRDH

tAVCS

tCSLWRL

tPWR

tWRHCSB

tWRLIORL

tPIOR

tCSLIOCS

tIORHWRH

tCSHIOCS

tDWS

tDWB

PC_A[2:0]

PC_CS

PC_WR

PC_ READY

PC_IO16

PC_D[15:0]

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