AD8331 datasheet(22/32 Pages) AD

22 / 32 page

AD8331/AD8332

Rev. C | Page 22 of 32

APPLICATIONS

LNA – EXTERNAL COMPONENTS

The LMD pin (connected to the bias circuitry) must be

bypassed to ground, and signal source to the INH pin

capacitively coupled using 2.2 nF to 0.1 μF capacitors (see

Figure 66).

The unterminated input impedance of the LNA is 6 kΩ. The

user may synthesize any LNA input resistance between 50 Ω

and 6 kΩ. RFB is calculated according to Equation 6 or selected

from Table .

()

–

Table 3. LNA External Component Values

for Common Source Impedances

RIN (Ω)

RFB (Nearest STD 1% Value, Ω)

CSH (pF)

280

412

100

562

200

1.13k

1.2

500

3.01k

None

∞

None

When active input termination is used, a 0.1 µF capacitor (CFB) is

required to isolate the input and output bias voltages of the LNA.

The shunt input capacitor, CSH, reduces gain peaking at higher

frequencies where the active termination match is lost due to

the HF gain roll-off of the LNA. Suggested values are shown in

Table ; for unterminated applications, reduce the capacitor value

by half.

When a long trace to Pin INH is unavoidable, or if both LNA

outputs drive external circuits, a small ferrite bead (FB) in series

with Pin INH preserves circuit stability with negligible effect on

noise. The bead shown is 75 Ω at 100 MHz (Murata BLM21 or

equivalent). Other values may prove useful.

Figure 67 shows the interconnection details of the LNA output.

Capacitive coupling between LNA outputs and the VGA inputs

is required because of differences in their dc levels and to

eliminate the offset of the LNA. Capacitor values of 0.1 µF are

recommended. There is 0.4 dB loss in gain between the LNA

output and the VGA input due to the 5 Ω output resistance.

Additional loading at the LOP and LON outputs will affect

LNA gain.

VCM2

RCLMP

COMM

VOL2

VOH2

VIP2

GAIN

VIN2

LOP2

COM2

LMD2

LON2

VPS2

INH2

COM1

LOP1

LMD1

LON1

VPS1

INH1

VOH1

ENB

VIP1

VCM1

VIN1

VPSV

VOL1

HILO

0.1 F

FB*

CLMD

0.1

µF

1nF

1n F

FB*

+5V

SH*

LNA

SOURCE

VGA OUT

1nF

0.1

µF

*SEE TEXT

LNA OUT

1nF

GAIN

1nF

0.1

µF

0.1

µF

0.1

µF

0.1

µF

1nF

0.1

µF

Figure 66. Basic Connections for a Typical Channel (AD8332 Shown)

Ω

LNA

VIN

VIP

LOP

VCM

100

Ω

LON

TO EXT

CIRCUIT

TO EXT

CIRCUIT

Ω

100

Ω

Figure 67. Interconnections of the LNA and VGA

Both LNA outputs are available for driving external circuits. Pin

LOP should be used in those instances when a single-ended

LNA output is required. The user should be aware of stray

capacitance loading of the LNA outputs, in particular LON. The

LNA can drive 100 Ω in parallel with 10 pF. If an LNA output is

routed to a remote PC board, it will tolerate a load capacitance

up to 100 pF with the addition of a 49.9 Ω series resistor or

ferrite 75 Ω/100 MHz bead.

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