S3A3 datasheet(89/139 Pages) RENESAS

89 / 139 page

R01DS0307EU0100 Rev.1.00

Page 89 of 139

Mar 7, 2017

S3A3

2. Electrical Characteristics

Figure 2.67

SPI timing (slave, CPHA = 1)

2.3.11

QSPI Timing

Note 1.

tPcyc: PCLKA cycle.

Note 2.

N is set to 0 or 1 in SFMSLD.

Note 3.

N is set to 0 or 1 in SFMSHD.

Note 4.

The upper limit of QSPCLK is 16MHz.

Table 2.41

QSPI timing

Conditions: VCC = 1.8 to 5.5 V

Conditions: Middle drive output is selected in the Port Drive Capability bit in PmnPFS register

Parameter

Symbol

Min

Max

Unit*1

Test conditions

QSPI

QSPCLK clock cycle

tQScyc

2*4

tPcyc

Figure 2.68

QSPCLK clock high-level pulse width

tQSWH

tQScyc × 0.4

QSPCLK clock low-level pulse width

tQSWL

tQScyc × 0.4

Data input setup time

tSU

Figure 2.69

Data input hold time

tIH

SSL setup time

tLEAD

(N + 0.5) ×

tQscyc - 15*2

(N + 0.5) ×

tQscyc + 100*2

SSL hold time

tLAG

(N + 0.5) ×

tQscyc - 15*3

(N + 0.5) ×

tQscyc + 100*3

Data output delay

2.7 V or above

tOD

-14

2.4 V or above

1.8 V or above

Data output hold time

2.7 V or above

tOH

–3.3

1.8 V or above

–10

Successive transmission delay

tTD

116

tQscyc

SSLA0

input

RSPCKA

CPOL = 0

input

RSPCKA

CPOL = 1

input

MISOA

output

MOSIA

input

tDr, tDf

tSA

tOH

tLEAD

tTD

tLAG

LSB OUT

(Last data)

DATA

MSB OUT

MSB IN

DATA

LSB IN

MSB IN

LSB OUT

tSU

tOD

tREL

MSB OUT

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