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WM8775EDS/R データシート(PDF) 17 Page - Wolfson Microelectronics plc

部品番号 WM8775EDS/R
部品情報  24 BIT 96 KHZ ADC WITH 4 CHANNEL I/P MULTIPLEXER
PDF  36 Pages
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メーカー  WOLFSON [Wolfson Microelectronics plc]
ホームページ  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8775EDS/R データシート(HTML) 17 Page - Wolfson Microelectronics plc

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WM8775
w
PP Rev 1.8, June 2004
17
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
DOUT
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
Figure 13 Right Justified Mode Timing Diagram
I
2S MODE
In I
2S mode, the MSB of the ADC data is output on DOUT and changes on the first falling edge of
BCLK following an ADCLRC transition and may be sampled on the rising edge of BCLK. ADCLRC is
low during the left samples and high during the right samples.
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
DOUT
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
1 BCLK
1 BCLK
Figure 14 I
2S Mode Timing Diagram
DSP EARLY MODE
The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of
BCLK following a low to high ADCLRC transition and may be sampled on the rising edge of BCLK.
The right channel ADC data is contiguous with the left channel data (Figure 15)
ADCLRC
BCK
DOUT
Word Length (WL)
1/fs
LEFT CHANNEL
n
2
1
n-1
LSB
MSB
n
2
1
n-1
RIGHT CHANNEL
NO VALID DATA
1 BCLK
1 BCLK
Figure 15 DSP Early Mode Timing Diagram – ADC Data Output



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