データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

WM8775EDS/R データシート(PDF) 29 Page - Wolfson Microelectronics plc

部品番号 WM8775EDS/R
部品情報  24 BIT 96 KHZ ADC WITH 4 CHANNEL I/P MULTIPLEXER
PDF  36 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  WOLFSON [Wolfson Microelectronics plc]
ホームページ  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8775EDS/R データシート(HTML) 29 Page - Wolfson Microelectronics plc

Back Button WM8775EDS/R Datasheet HTML 25Page - Wolfson Microelectronics plc WM8775EDS/R Datasheet HTML 26Page - Wolfson Microelectronics plc WM8775EDS/R Datasheet HTML 27Page - Wolfson Microelectronics plc WM8775EDS/R Datasheet HTML 28Page - Wolfson Microelectronics plc WM8775EDS/R Datasheet HTML 29Page - Wolfson Microelectronics plc WM8775EDS/R Datasheet HTML 30Page - Wolfson Microelectronics plc WM8775EDS/R Datasheet HTML 31Page - Wolfson Microelectronics plc WM8775EDS/R Datasheet HTML 32Page - Wolfson Microelectronics plc WM8775EDS/R Datasheet HTML 33Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 29 / 36 page
background image
Product Preview
WM8775
w
PP Rev 1.8, June 2004
29
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R7 (07h)
0000111
Timeout Clock
Disable
3
TOD
0
ADC Analogue PGA Zero cross detect timeout disable
0 : Timeout enabled
1: Timeout disabled
1:0
ADCFMT[1:0]
10
Interface format select
00: right justified mode
01: left justified mode
10: I
2S mode
11: DSP mode
ADCLRC Polarity or DSP Early/Late mode select
2
ADCLRP
0
In left/right/ I
2S modes:
ADCLRC Polarity (normal)
0 : normal ADCLRC polarity
1: inverted ADCLRC polarity
DSP Mode
0: Early DSP mode
1: Late DSP mode
3
ADCBCP
0
BITCLK Polarity
0: Normal - ADCLRC sampled on rising edge of BCLK;
DOUT changes on falling edge of BCLK.
1: Inverted - ADCLRC sampled on falling edge of BCLK;
DOUT changes on rising edge of BCLK.
5:4
ADCWL[1:0]
10
Input Word Length
00: 16-bit Mode
01: 20-bit Mode
10: 24-bit Mode
11: 32-bit Mode (not supported in right justified mode)
6
ADCMCLK
0
ADCMCLK Polarity
0 : non-inverted
1: inverted
R11 (0Bh)
0001011
Interface
Control
8
ADCHPD
0
ADC High pass Filter Disable:
0: High pass Filter enabled
1: High pass Filter disabled
2:0
ADCRATE[2:0]
010
Master Mode MCLK:ADCLRC ratio select:
010: 256fs
011: 384fs
100: 512fs
101: 768fs
3
ADCOSR
0
ADC oversample rate select
0: 128x oversampling
1: 64x oversampling
12 (0Ch)
0001100
Master Mode
Control
8
ADCMS
0
Maser/Slave interface mode select
0: Slave Mode – ADCLRC and BCLK are inputs
1: Master Mode – ADCLRC and BCLK are outputs
0
PWDN
0
Chip Powerdown Control (works together with ADCD):
0: All circuits running, outputs are active
1: All circuits in power save mode, outputs muted
1
ADCPD
0
ADC powerdown:
0: ADC enabled
1: ADC disabled
R13 (0Dh)
0001101
Powerdown
Control
6
AINPD
0
Input mux and buffer powerdown
0: Input mux and buffer enabled
1: Input mux and buffer powered down



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com