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WM8978GEFL/V データシート(PDF) 26 Page - Wolfson Microelectronics plc

部品番号 WM8978GEFL/V
部品情報  STEREO CODEC WITH SPEAKER DRIVER
PDF  78 Pages
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メーカー  WOLFSON [Wolfson Microelectronics plc]
ホームページ  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8978GEFL/V データシート(HTML) 26 Page - Wolfson Microelectronics plc

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WM8978
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PP Rev 1.7 January 2005
26
PROGRAMMABLE NOTCH FILTER
A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth,
programmable via two coefficients, a0 and a1.
a0 and a1 are represented by the register bits
NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four register writes to setup
there is an NFU (Notch Filter Update) flag which should be set only when all four registers are setup.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
6:0
NFA0[6:0]
0
Notch Filter a0 coefficient, bits [6:0]
7
NFEN
0
Notch filter enable:
0=Disabled
1=Enabled
R27
Notch Filter 1
8
NFU
0
Notch filter update. The notch filter
values used internally only update
when one of the NFU bits is set high.
6:0
NFA0[13:7]
0
Notch Filter a0 coefficient, bits [13:7]
R28
Notch Filter 2
8
NFU
0
Notch filter update. The notch filter
values used internally only update
when one of the NFU bits is set high.
6:0
NFA1[6:0]
0
Notch Filter a1 coefficient, bits [6:0]
R29
Notch Filter 3
8
NFU
0
Notch filter update. The notch filter
values used internally only update
when one of the NFU bits is set high.
0-6
NFA1[13:7]
0
Notch Filter a1 coefficient, bits [13:7]
R30
Notch Filter 4
8
NFU
0
Notch filter update. The notch filter
values used internally only update
when one of the NFU bits is set high.
Table 14 Notch Filter Function
The coefficients are calculated as follows:
)
2
/
tan(
1
)
2
/
tan(
1
0
b
b
w
w
a
+
−
=
)
cos(
)
1
(
0
0
1
w
a
a
+
−
=
Where:
s
c
f
f
w
/
2
0
π
=
s
b
b
f
f
w
/
2
π
=
fc = centre frequency in Hz, fb = -3dB bandwidth in Hz, fs = sample frequency in Hz
The actual register values can be determined from the coefficients as follows:
NFA0 = -a0 x 2
13
NFA1 = -a1 x 2
12
DIGITAL ADC VOLUME CONTROL
The output of the ADCs can be digitally attenuated over a range from –127dB to 0dB in 0.5dB steps.
The gain for a given eight-bit code X is given by:
0.5
× (G-255) dB for 1 ≤ G ≤ 255;
MUTE for G = 0



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