HT27C010

Rev. 1.10

5

November 21, 2002

Functional Description

Programming of the HT27C010

When the HT27C010 is delivered, the chip has all

1024K bits in the

²ONE², or HIGH state. ²ZEROs² are

loaded into the HT27C010 through programming.

The programming mode is entered when 12.5

±0.2V is ap-

plied with 8 bits in parallel to the data pins.

The programming flowchart in Figure 3 shows the fast

interactive programming algorithm. The interactive al-

gorithm reduces programming time by using 30

msto

105

ms programming pulses and giving each address

only as many pulses as is necessary in order to reliably

program the data. After each pulse is applied to a given

address, the data in that address is verified. If the data

is not verified, additional pulses are given until it is veri-

fied or until the maximum number of pulses is reached

while sequencing through each address of the

HT27C010. This process is repeated while sequencing

through each address of the HT27C010. This part of

sure that each EPROM bit is programmed to a suffi-

ciently high threshold voltage. This ensures that all bits

have sufficient margin. After the final address is com-

pleted, the entire EPROM memory is read at

±0.25V to verify the entire memory.

Program inhibit mode

Programming of multiple HT27C010 in parallel with dif-

ferent data is also easily accomplished by using the Pro-

gram Inhibit Mode. Except for CE, all like inputs of the

parallel HT27C010 may be common. A TTL low-level

program pulse applied to an HT27C010 CE input with

±0.2V, PGM LOW, and OE HIGH will program

that HT27C010. A high-level CE input inhibits the

HT27C010 from being programmed.

Program verify mode

Verification should be performed on the programmed

bits to determine whether they were correctly pro-

grammed. The verification should be performed with OE

voltage.

Auto product identification

The Auto Product Identification mode allows the reading

out of a binary code from an EPROM that will identify its

manufacturer and the type. This mode is intended for

programming to automatically match the device to be

programmed with its corresponding programming algo-

rithm. This mode is functional in the 25

°C±5°C ambient

temperature range that is required when programming

the HT27C010.

To activate this mode, the programming equipment

must force 12.0

±0.5V on the address line A9 of the

HT27C010. Two identifier bytes may then be se-

quenced from the device outputs by toggling address

mode.

two identifier bytes are given in the Operation mode truth

table. All identifiers for the manufacturer and device codes

will possess odd parity, with the MSB (DQ7) defined as the

nary code of 7F, continuation code, to signify the unavail-

ability of manufacturer ID codes.

Read mode

The HT27C010 has two control functions, both of which

must be logically satisfied in order to obtain data at out-

puts. Chip Enable (CE) is the power control and should

be used for device selection. Output Enable (OE)isthe

output control and should be used to gate data to the

output pins, independent of device selection. Assuming

suming the CE has been LOW and addresses have

Standby mode

The HT27C010 has CMOS standby mode which re-

duces the maximum VCC current to 10

mA. It is placed in

±0.3V. The

HT27C010 also has a TTL-standby mode which re-

duces the maximum VCC current to 1.0mA. It is placed

mode, the outputs are in a high-impedance state, inde-

pendent of the OE input.

Two-line output control function

To accommodate multiple memory connections, a

two-line control function is provided to allow for:

It is recommended that CE be decoded and used as the

primary device-selection function, while OE be made a

common connection to the READ line from the system

control bus. This assures that all deselected memory

devices are in their low-power standby mode and that

the output pins are only active when data is desired from

a particular memory device.