AD9637_17 datasheet(10/41 Pages) AD

10 / 41 page

Data Sheet

AD9637

Rev. A | Page 9 of 40

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVDD

VIN+ G

VIN– G

AVDD

VIN– H

VIN+ H

AVDD

CLK–

CLK+

AVDD

DNC

DRVDD

D– H

D+ H

AVDD

VIN+ B

VIN– B

AVDD

VIN– A

VIN+ A

AVDD

PDWN

CSB

SDIO/DFS

SCLK/DTP

AVDD

DNC

DRVDD

D+ A

D– A

AD9637

TOP VIEW

(Not to Scale)

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.

PIN 1

INDICATOR

Figure 5. Pin Configuration, Top View

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

0, EP

AGND,

Exposed Pad

Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the

analog ground for the part. This exposed pad must be connected to analog ground for proper operation.

1, 4, 7, 8, 11,

12, 37, 42, 45,

48, 51, 59, 62

AVDD

1.8 V Analog Supply.

13, 36

DNC

Do Not Connect. Do not connect to this pin.

14, 35

DRVDD

1.8 V Digital Output Driver Supply.

2, 3

VIN+ G, VIN− G

ADC G Analog Input True, ADC G Analog Input Complement.

5, 6

VIN− H, VIN+ H

ADC H Analog Input Complement, ADC H Analog Input True.

9, 10

CLK−, CLK+

Input Clock Complement, Input Clock True.

15, 16

D− H, D+ H

ADC H Digital Output Complement, ADC H Digital Output True.

17, 18

D− G, D+ G

ADC G Digital Output Complement, ADC G Digital Output True.

19, 20

D− F, D+ F

ADC F Digital Output Complement, ADC F Digital Output True.

21, 22

D− E, D+ E

ADC E Digital Output Complement, ADC E Digital Output True.

23, 24

DCO−, DCO+

Data Clock Digital Output Complement, Data Clock Digital Output True.

25, 26

FCO−, FCO+

Frame Clock Digital Output Complement, Frame Clock Digital Output True.

27, 28

D− D, D+ D

ADC D Digital Output Complement, ADC D Digital Output True.

29, 30

D− C, D+ C

ADC C Digital Output Complement, ADC C Digital Output True.

31, 32

D− B, D+ B

ADC B Digital Output Complement, ADC B Digital Output True.

33, 34

D− A, D+ A

ADC A Digital Output Complement, ADC A Digital Output True.

SCLK/DTP

Serial Clock (SCLK)/Digital Test Pattern (DTP).

SDIO/DFS

Serial Data Input/Output (SDIO)/Data Format Select (DFS).

CSB

Chip Select Bar.

PDWN

Power-Down.

43, 44

VIN+ A, VIN− A

ADC A Analog Input True, ADC A Analog Input Complement.

46, 47

VIN− B, VIN+ B

ADC B Analog Input Complement, ADC B Analog Input True.

49, 50

VIN+ C, VIN− C

ADC C Analog Input True, ADC C Analog Input Complement.

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