AD9601_17 datasheet(6/33 Pages) AD

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AD9601

Rev. 0 | Page 5 of 32

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.

Table 3.

AD9601-200

AD9601-250

Parameter1

Temp

Min

Typ

Max

Min

Typ

Max

Unit

CLOCK INPUTS

Logic Compliance

Full

CMOS/LVDS/LVPECL

Internal Common-Mode Bias

Full

1.2

Differential Input Voltage

Full

0.2

V p-p

Input Voltage Range

Full

AVDD − 0.3

AVDD + 1.6

AVDD − 0.3

AVDD + 1.6

Input Common-Mode Range

Full

1.1

AVDD

1.1

AVDD

High Level Input Voltage (VIH)

Full

1.2

3.6

1.2

3.6

Low Level Input Voltage (VIL)

Full

0.8

Input Resistance (Differential)

Full

kΩ

Input Capacitance

Full

LOGIC INPUTS

Logic 1 Voltage

Full

0.8 × VDD

Logic 0 Voltage

Full

0.2 × AVDD

Logic 1 Input Current (SDIO)

Full

μA

Logic 0 Input Current (SDIO)

Full

−60

μA

Logic 1 Input Current

(SCLK, PDWN, CSB, RESET)

Full

μA

Logic 0 Input Current

(SCLK, PDWN, CSB, RESET)

Full

μA

Input Capacitance

25°C

LOGIC OUTPUTS

High Level Output Voltage

Full

DRVDD − 0.05

Low Level Output Voltage

Full

GND + 0.05

Output Coding

Twos complement, Gray code, or offset binary (default)

1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

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