AD7643BSTZ datasheet(16/29 Pages) AD

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AD7643

Rev. 0 | Page 15 of 28

APPLICATIONS INFORMATION

SW+

COMP

SW–

IN+

REF

REFGND

LSB

MSB

131,072C

65,536C

CONTROL

LOGIC

SWITCHES

CONTROL

BUSY

OUTPUT

CODE

CNVST

IN–

LSB

MSB

AGND

131,072C 65,536C

Figure 21. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7643 is a very fast, low power, single-supply, precise

18-bit ADC using successive approximation architecture. The

AD7643 is capable of converting 1,250,000 samples per second

(1.25 MSPS).

The AD7643 provides the user with an on-chip, track-and-hold,

successive approximation ADC that does not exhibit any

pipeline or latency, making it ideal for multiple multiplexed

channel applications.

The AD7643 can operate from a single 2.5 V supply and

interface to either 5 V, 3.3 V, or 2.5 V digital logic. It is housed

in a Pb-free, 48-lead LQFP package or a tiny 48-lead LFCSP

package, which combines space savings with flexibility and

allows the AD7643 to be configured as either a serial or a

parallel interface. The AD7643 is pin-to-pin compatible with

the AD7641 and is a speed upgrade of the AD7674, AD7678,

and AD7679.

CONVERTER OPERATION

The AD7643 is a successive approximation ADC based on a

charge redistribution DAC. Figure 21 shows the simplified

schematic of the ADC. The capacitive DAC consists of two

identical arrays of 16 binary weighted capacitors that are

connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the

comparator’s input are connected to AGND via SW+ and SW−.

All independent switches are connected to the analog inputs.

Therefore, the capacitor arrays are used as sampling capacitors

and acquire the analog signal on the IN+ and IN− inputs. A

conversion phase is initiated once the acquisition phase is complete

and the CNVST input goes low. When the conversion phase

begins, SW+ and SW− are opened first. The two capacitor

arrays are then disconnected from the inputs and connected to

the REFGND input. Therefore, the differential voltage between

the inputs (IN+ and IN−) captured at the end of the acquisition

phase is applied to the comparator inputs, causing the

comparator to become unbalanced. By switching each element

of the capacitor array between REFGND and REF, the comparator

input varies by binary weighted voltage steps (VREF/2, VREF/4

throughVREF/262144). The control logic toggles these switches,

starting with the MSB first, to bring the comparator back into a

balanced condition. After the completion of this process, the

control logic generates the ADC output code and brings BUSY

output low.

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