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MSP432P411VIPZ データシート(PDF) 156 Page - Texas Instruments

部品番号 MSP432P411VIPZ
部品情報  SimpleLink Mixed-Signal Microcontrollers
PDF  212 Pages
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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MSP432P411VIPZ データシート(HTML) 156 Page - Texas Instruments

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MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
Submit Documentation Feedback
Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V
Detailed Description
Copyright © 2017–2018, Texas Instruments Incorporated
(1)
X = Don't care
(2)
Not available on the 64-pin RGC package.
(3)
Direction controlled by eUSCI_A3 module.
(4)
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
6.12.4 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
Port Schematic: see Figure 6-8
Table 6-66 lists the settings to select the port functions.
Table 6-66. Port P9 (P9.4 to P9.7) Pin Functions
PIN NAME (P9.x)
x
FUNCTION
CONTROL BITS OR SIGNALS (1)
P9DIR.x
P9SEL1.x
P9SEL0.x
P9.4/UCA3STE/L43 (2)
4
P9.4 (I/O)
I: 0; O: 1
0
0
UCA3STE
X (3)
0
1
L43 (4)
X
1
0
N/A
0
1
1
DVSS
1
P9.5/UCA3CLK/L42 (2)
5
P9.5 (I/O)
I: 0; O: 1
0
0
UCA3CLK
X (3)
0
1
L42 (4)
X
1
0
N/A
0
1
1
DVSS
1
P9.6/UCA3RXD/UCA3SOMI/L4
1 (2)
6
P9.6 (I/O)
I: 0; O: 1
0
0
UCA3RXD/UCA3SOMI
X (3)
0
1
L41 (4)
X
1
0
N/A
0
1
1
DVSS
1
P9.7/UCA3TXD/UCA3SIMO/L4
0 (2)
7
P9.7 (I/O)
I: 0; O: 1
0
0
UCA3TXD/UCA3SIMO
X (3)
0
1
L40 (4)
X
1
0
N/A
0
1
1
DVSS
1



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