SLG46121V datasheet(7/98 Pages) DIALOG

7 / 98 page

000-0046121--106

Page 6 of 97

SLG46121

VOL

LOW-Level Output Voltage

PIN 2, 3, 4, 5, 6

Push-Pull 1X,

IOL= 100 A

0.020

0.030

Push-Pull 2X,

IOL= 100 A

0.010

0.020

Open Drain NMOS 1X,

IOL= 100 A

0.010

0.020

Open Drain NMOS 2X,

IOL= 100 A

0.010

IOH

HIGH-Level Output Current

(see Note 1)

PIN 2, 3, 4, 5, 6

Push-Pull 1X, Open Drain PMOS 1X,

VOH = VDD - 0.2

1.000

1.390

Push-Pull 2X, Open Drain PMOS 2X,

VOH = VDD - 0.2

2.100

2.680

IOL

LOW-Level Output Current

(see Note 1)

PIN 2, 3, 4, 5, 6

Push-Pull 1X,

VOL = 0.15 V

0.760

1.340

Push-Pull 2X,

VOL = 0.15 V

1.520

2.660

Open Drain NMOS 1X,

VOL = 0.15 V

1.530

2.670

Open Drain NMOS 2X,

VOL = 0.15 V

3.060

5.136

IVDD

Maximum Average or DC

Current Through VDD Pin

(Per chip side, see Note 2)

TJ = 85°C

TJ = 110°C

IGND

Maximum Average or DC

Current Through GND Pin

(Per chip side, see Note 2)

TJ = 85°C

TJ = 110°C

TSU

Startup Time

from VDD rising past 1.35 V

0.31

PONTHR

Power On Threshold

VDD Level Required to Start Up the

Chip

1.180

1.353

1.516

POFFTHR Power Off Threshold

VDD Level Required to Switch Off the

Chip

0.730

0.914

1.103

RPUP

Pull Up Resistance

1 M Pull Up

975.92

1061.05

1132.72



100 k Pull Up

99.56

107.15

114.11



10 k Pull Up

11.51

12.86

14.36



RPDWN

Pull Down Resistance

1 M Pull Down

975.32

1061.05

1133.17



100 k Pull Down

100.43

107.26

114.05



10 k Pull Down

11.17

12.48

13.86



Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.

Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5 and 6 are connected to one side, pins 8, 9, 10 and

12 to another.

Symbol

Parameter

Condition/Note

Min.

Typ.

Max.

Unit

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