ACE24AC02A3C

Two-wire Serial EEPROM

VER 1.1

4

Memory Organization

The ACE24AC02A3C devices have 16 pages. Since each page has 16 bytes, random word addressing to

ACE24AC02A3C will require 8 bits data word addresses.

Device Operation

(A)

Serial Clock And Data Transitions

The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when

Serial clock SCL is at VIL. Any SDA signal transition may interpret as either a START or STOP

condition as described below.

(B)

Start Condition

With SCL ≥ VIH, a SDA transition from high to low is interpreted as a START condition. All valid

commands must begin with a START condition.

(C)

Stop Condition

With SCL ≥ VIH, a SDA transition from low to high is interpreted as a STOP condition. All valid read

or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after

a read command.

A STOP condition after page or byte write command will trigger the chip into the STANDBY mode

after the self- timed internal programming finish.

(D)

Acknowledge

The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The

EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The

ACKNOWLEDGE signal occurs on the 9th serial clock after each word.

(E)

Standby Mode

The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP

bit in read mode, or after completing a self-time internal programming operation.

Figure 3: Timing diagram for start and stop conditions