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AM652X データシート(PDF) 188 Page - Texas Instruments |
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AM652X データシート(HTML) 188 Page - Texas Instruments |
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188 / 299 page  D3 D1 CS# RESET# HYPERBUS_TIMING_03 HYPERBUS_TIMING_02 RWDS DQ[7:0] Command-Address Host drives DQ[7:0] and Memory drives RWDS CK and Data are center aligned Host drives DQ[7:0] and RWDS 39:32 31:24 23:16 15:8 7:0 47:40 Dn Dn Dn+1 Dn+1 A B A B CK, CK# CS# D8/LFD8 D2 D9/LFD9 D7/LFD7 D6/LFD6 D10/LFD10 D4 D12/LFD12 D5/LFD5 D5/LFD5 188 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated Figure 5-59. HyperBus Timing Diagrams - Receiver Mode Figure 5-60. HyperBus Timing Diagrams - Reset For more information, see section Hyperbus Interface in chapter Memory Interfaces of the Device TRM. 5.11.5.12 I2C For more details about features and additional description information on the device Inter-Integrated Circuit, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. Table 5-57, and Figure 5-61 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 5-57. Timing Requirements for I2C Input Timings(1)(6) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT I1 tc(SCL) Cycle time, SCL Standard 10000 ns Fast 2500 ns I2 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) Standard 4700 ns Fast 600 ns I3 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) Standard 4000 ns Fast 900 ns I4 tw(SCLL) Pulse duration, SCL low Standard 4700 ns Fast 1300 ns I5 tw(SCLH) Pulse duration, SCL high Standard 4000 ns Fast 600 ns I6 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high Standard 250 ns Fast 100(2) ns I7 th(SCLL-SDAV) Hold time, SDA valid after SCL low Standard 0(3) 3450(4) ns Fast 0(3) 900(4) ns |
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