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AM652X データシート(PDF) 189 Page - Texas Instruments |
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AM652X データシート(HTML) 189 Page - Texas Instruments |
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189 / 299 page  I10 I8 I4 I3 I7 I12 I5 I6 I14 I2 I3 I13 Stop Start Repeated Start Stop I2Cx_SDA I2Cx_SCL I1 I11 I9 189 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated Table 5-57. Timing Requirements for I2C Input Timings(1)(6) (continued) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT I8 tw(SDAH) Pulse duration, SDA high between STOP and START conditions Standard 4700 ns Fast 1300 ns I9 tr(SDA) Rise time, SDA Standard 1000 ns Fast 20+.1Cb(5) (7) 300(3) (7) ns I10 tr(SCL) Rise time, SCL Standard 1000 ns Fast 20+.1Cb(5) (7) 300(3) (7) ns I11 tf(SDA) Fall time, SDA Standard 300 ns Fast 20+.1Cb(5) (7) 300(3) (7) ns I12 tf(SCL) Fall time, SCL Standard 300 ns Fast 20+.1Cb 300 ns I13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) Standard 4000 ns Fast 600 ns I14 tw(SP) Pulse duration, spike (must be supressed) Standard ns Fast 0 50 ns I15 tskew Skew Standard 1 ns Fast 1 ns I16 Cb Capacitive load for each bus line Standard 400 pF Fast 400 pF (1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the devive is powered down. (2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released. (3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. (4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. (5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed (6) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the Device TRM for details. (7) These timings apply only to MCU_I2C0 and WKUP_I2C0. MAIN_I2C[0:3] use standard LVCMOS buffers to emulate open-drain buffers and their rise/fall times should be referenced in the device IBIS model. Figure 5-61. I2C Receive Timing(1) (1) x in I2Cx_SDA and I2Cx_SCL is 0, 1 or 2. |
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