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AD5721 データシート(PDF) 18 Page - Analog Devices |
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AD5721 データシート(HTML) 18 Page - Analog Devices |
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18 / 31 page ![]() AD5761/AD5721 Data Sheet Rev. C | Page 18 of 32 SCLK SDI 200µs/DIV 5V 5V 2V 5V SYNC VOUT Figure 55. Software Full Reset Glitch from Zero Scale with Output Loaded, ±10 V Range 200µs/DIV 5V 5V 1V 5V SCLK SYNC SDI VOUT Figure 56. Output Range Change Glitch, 0 V to 5 V Range 200µs/DIV 5V 5V 200mV 5V SCLK SYNC SDI VOUT Figure 57. Output Range Change Glitch, ±10 V Range –4 –2 0 2 4 6 8 10 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 TIME (Seconds) VDD = +21V VSS = –11V VREFIN = 2.5V TA = 25°C Figure 58. Peak-to-Peak Noise (Voltage Output Noise), 0.1 Hz to 10 Hz Bandwidth –30 –20 –10 0 10 20 30 –2.0 2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 TIME (Seconds) VDD = +21V VSS = –11V TA = 25°C Figure 59. Peak-to-Peak Noise (Voltage Output Noise), 100 kHz Bandwidth FREQUENCY (Hz) DAC OUTPUT NSD (nV/√Hz), EXT REF, ZS DAC OUTPUT NSD (nV/√Hz), EXT REF, MS DAC OUTPUT NSD (nV/√Hz), EXT REF, FS VDD = +21V VSS = –11V TA = 25°C Figure 60. DAC Output Noise Spectral Density vs. Frequency, ±10 V Range |
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