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ADM1266ACPZ-R7 データシート(PDF) 10 Page - Analog Devices

部品番号 ADM1266ACPZ-R7
部品情報  Cascadable Super Sequencer Margin Control and Fault Recording
PDF  62 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

ADM1266ACPZ-R7 データシート(HTML) 10 Page - Analog Devices

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ADM1266
Data Sheet
Rev. A | Page 10 of 62
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Rating
VHx, PDIOx to GND
21 V
VPx, AVDD_CAP to GND
5.5 V
DACx to GND
3.6 V
REFOUT to GND
3.6 V
ADDR to GND
3.6 V
REFGND, EPAD to GND
−0.3 V to +0.3 V
All Other Pins to GND
3.6 V
Maximum Junction Temperature (TJ max)
150°C
Storage Temperature Range1
−65°C to +125°C
ESD Rating, All Pins
Charged Device Model
750 V
Human Body Model
2000 V
1 See the Acceleration Factor section.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal resistance
measured in a one cubic foot sealed enclosure. The thermal
resistance values specified in Table 5 are calculated based on
JEDEC specs and must be used in compliance with JESD51-12.
Table 5. Thermal Resistance1
Package Type
θJA2
θJC_BOTTOM3, 4
ΨJT
ΨJB
Unit
CP-64-15
24.2
0.6
0.1
3.6
˚C/W
1 The values in Table 5 are calculated based on standard JEDEC test conditions,
unless otherwise specified
2 θJA is simulated using a 2S2P PCB with 49 standard JEDEC vias.
3 For the θJC_BOTTOM test, 100 µm TIM is used. TIM is assumed to have 3.6 W/mK.
4 θJC_BOTTOM is simulated using a 1S0P PCB with 49 standard JEDEC vias.
ESD CAUTION



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