GPR25L081B datasheet(16/37 Pages) GENERALPLUS

16 / 37 page

GPR25L081B

Proprietary & Confidential

DEC. 15, 2010

Version: 1.1

While Program/Erase operation is in progress, it will not decode

the RDID instruction, so there's no effect on the cycle of

program/erase operation which is currently in progress.

When

CS# goes high, the device is at standby stage.

10.15.Read Electronic Manufacturer ID & Device ID

(REMS)

The REMS instruction is an alternative to the Release from

Power-down/Device ID instruction that provides both the JEDEC

assigned manufacturer ID and the specific device ID.

The REMS instruction is very similar to the Release from

Power-down/Device ID instruction.

The instruction is initiated by

driving the CS# pin low and shift the instruction code "90h" or

"EFh" followed by two dummy bytes and one bytes address

(A7~A0).

After which, the Manufacturer ID and the Device ID are

shifted out on the fallingedge of SCLK with most significant bit

(MSB) first as shown in figure 26.

The Device ID values are

listed in Table of ID Definitions.

If the one-byte address is initially

set to 01h, then the device ID will be read first and then followed

by the Manufacturer ID.

The Manufacturer and Device IDs can

be read continuously, alternating from one to the other.

The

instruction is completed by driving CS# high.

Table6. ID Definitions

Command Type

GPR25L081B

manufacturer ID

memory type

memory density

RDID Command

electronic ID

RES Command

manufacturer ID

device ID

REMS

10.16.Enter Secured OTP (ENSO)

The ENSO instruction is for entering the additional 512 bit secured

OTP mode.

The additional 512 bit secured OTP is independent

from main array, which may use to store unique serial number for

system identifier.

After entering the Secured OTP mode, and

then follow standard read or program, procedure to read out the

data or update data.

The Secured OTP data cannot be updated

again once it is lock-down.

Please note that WRSR/WRSCUR commands are not acceptable

during the access of secure OTP region, once security OTP is lock

down, only read related commands are valid.

10.17.Exit Secured OTP (EXSO)

The EXSO instruction is for exiting the additional 512 bit secured

OTP mode.

10.18.Read Security Register (RDSCUR)

The RDSCUR instruction is for reading the value of Security

The Read Security Register can be read at any

time (even in program/erase/write status register/write security

The definition of the Security Register bits is as below:

Secured OTP Indicator bit. The Secured OTP indicator bit shows

the chip is locked by factory before ex- factory or not.

When it is

"0", it indicates non- factory lock; "1" indicates factory- lock.

Lock-down Secured OTP (LDSO) bit. By writing WRSCUR

instruction, the LDSO bit may be set to "1" for customer lock-down

purpose.

However, once the bit is set to "1" (lock-down), the

LDSO bit and the 512 bit Secured OTP area cannot be update any

more.

While it is in 512 bit secured OTP mode, array access is

not allowed.

Table7. Security Register Definition

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

LDSO (indicate if lock-down)

Secured OTP indicator bit

reserved

0 = not lockdown

1 = lock-down

(cannot program/erase OTP)

0 = nonfactory lock

1 = factory lock

volatile bit

non-volatile bit

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