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GPR25L081B データシート(PDF) 23 Page - Generalplus Technology Inc. |
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GPR25L081B データシート(HTML) 23 Page - Generalplus Technology Inc. |
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23 / 37 page  GPR25L081B © Generalplus Technology Inc. Proprietary & Confidential 23 DEC. 15, 2010 Version: 1.1 12.4. AC Characteristics Symbol Alt. Parameter Min. Typ. Max. Unit fSCLK fC Clock Frequency for the following instructions: FAST_READ, PP, SE, BE, CE, DP, RES, RDP, WREN, WRDI, RDID, RDSR, WRSR 10KHz - 86 MHz fRSCLK fR Clock Frequency for READ instructions 10KHz - 33 MHz fTSCLK fT Clock Frequency for 2READ instructions 10KHz - 80 MHz fC=86MHz 5.5 - - ns tCH(1) tCLH Clock High Time fR=33MHz 13 - - ns fC=86MHz 5.5 - - ns tCL(1) tCLL Clock Low Time fR=33MHz 13 - - ns tCLCH(2) Clock Rise Time (3) (peak to peak) 0.1 - - V/ns tCHCL(2) Clock Fall Time (3) (peak to peak) 0.1 - - V/ns tSLCH tCSS CS# Active Setup Time (relative to SCLK) 5 - - ns tCHSL CS# Not Active Hold Time (relative to SCLK) 5 - - ns tDVCH tDSU Data In Setup Time 2 - - ns tCHDX tDH Data In Hold Time 5 - - ns tCHSH CS# Active Hold Time (relative to SCLK) 5 - - ns tSHCH CS# Not Active Setup Time (relative to SCLK) 5 - - ns Read 15 - - ns tSHSL tCSH CS# Deselect Time Write 40 - - ns tSHQZ(2) tDIS Output Disable Time - - 6 ns tCLQV tV Clock Low to Output Valid, Loading 30pF/15pF - - 8/6 ns tCLQX tHO Output Hold Time 0 - - ns tHLCH HOLD# Setup Time (relative to SCLK) 5 - - ns tCHHH HOLD# Hold Time (relative to SCLK) 5 - - ns tHHCH HOLD Setup Time (relative to SCLK) 5 - - ns tCHHL HOLD Hold Time (relative to SCLK) 5 - - ns tHHQX(2) tLZ HOLD to Output Low-Z - - 6 ns tHLQZ(2) tHZ HOLD# to Output High-Z - - 6 ns tWHSL(4) Write Protect Setup Time 20 - - ns tSHWL (4) Write Protect Hold Time 100 - - ns tDP(2) CS# High to Deep Power-down Mode - - 10 us tRES1(2) CS# High to Standby Mode without Electronic Signature Read - - 8.8 us tRES2(2) CS# High to Standby Mode with Electronic Signature Read - - 8.8 us tW Write Status Register Cycle Time - 40 100 ms tBP Byte-Program - 9 300 us tPP Page Program Cycle Time - 1.4 5 ms tSE Sector Erase Cycle Time - 60 300 ms tBE Block Erase Cycle Time - 0.7 2 s tCE Chip Erase Cycle Time - 7 15 s Notes: 1. tCH + tCL must be greater than or equal to 1/ fC. For Fast Read, tCL/tCH=5.5/5.5. 2. Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 5. Test condition is shown as Figure 5. |
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