AM79C987 datasheet(8/30 Pages) AMD

8 / 30 page

AMD

P R E L I M I N A R Y

Am79C987

Microprocessor Interface

Access to the HIMIB device’s on-chip registers is made

via its simple processor interface which is designed to

be used by a variety of available microprocessors. The

bus interface is designed to be asynchronous and can

be easily adapted for different hardware interfaces.

The interface protocol is as follows:

Assert

CS (LOW) and C/D (HIGH to access Control

and LOW to access Data)

Assert

RD (LOW) to start a Read cycle or WR (LOW)

to start a Write cycle

The HIMIB device forces RDY LOW in response to

the falling edge of either of

RD or WR

Note:

CS is internally gated with RD and WR, such that

CS may be permanently grounded, if not required. The

start of Read or Write cycle is the time when

CS and

either

RD or WR strobes are both asserted (LOW).

Write Cycle:

Data is to be placed on the Data (D7–0) pins prior to

rising edge of

The HIMIB device releases RDY (pulled high exter-

nally), indicating that it is ready to latch the data

WR strobe is de-asserted (HIGH) in response to

RDY. The HIMIB chip latches data internally on ris-

ing edge of

The processor can stop driving the Data pins after

the rising edge of

Read Cycle:

The HIMIB device drives the Data (D7–0) pins

The HIMIB device releases RDY (pulled high exter-

nally), indicating valid data

RD strobe is de-asserted (HIGH) in response to

RDY. The external device should latch the HIMIB

chip’s data on the rising edge of

RD.

The HIMIB device stops driving the Data pins after

the rising edge of

Typically, Read and Write cycles take 500 ns (10 CK

clock cycles) to complete.

Upon reset, the Interrupt pin (

INT) is not driven, all inter-

nal sources of interrupts are cleared and all interrupts

are disabled (masked). Use of the

INT pin requires ex-

plicit enabling by setting the appropriate enable bits.

The

INT pin is driven low when any of the enabled inter-

rupts occur.

The

INT pin will go inactive after the internal source(s) of

the interrupt are cleared by reading the corresponding

Status registers.

All HIMIB internal registers are accessed by reading or

writing to or from two externally visible ports. These are

the Command Port (C Port) and the Data Port (D Port).

The C Port is accessed by asserting C/

D pin HIGH dur-

ing read or write accesses. The D Port is accessed by

driving the C/

D pin LOW during Read/Write access to

the HIMIB device.

As the C/

D pin is the only “address” line provided on the

HIMIB device bus interface, the internal register to be

accessed must be selected by writing its ”address” into

the Command Port.

The address appears to the programmer as two regis-

ters referred to as the P and R registers, both of which

are accessed via the Command Port. The P register se-

lects the register Port Number (or Bank Number), and is

accessed by writing a byte with the three most signifi-

cant bits set to zero into the C Port. The R register se-

lects the Register Number (or Attribute Number), and is

accessed by writing a byte with the three most signifi-

cant bits set to one into the C Port.

Once the C Port is programmed with a valid Port (Bank)

and Register (Attribute) Number, the entire 32-bit attrib-

ute is transferred to a holding register upon reading the

first byte. Subsequent accesses to the D Port access the

value in a least significant to most significant byte order.

When reading, once the last byte is read, the attribute

value is re-transferred to the holding register and the se-

quence can be restarted.

When the C Port is programmed for access to these

multi-byte registers, reading the D Port causes the value

of the register to be copied into the holding register. The

data is then read out from the holding register. This se-

quence is repeated until the last byte is read and the D

Port is accessed again. When the C Port is (re)pro-

grammed, the first byte read from the D Port will be the

least significant byte.

Note that the P and R registers can be accessed in any

sequence prior to accessing the D Port. If either P or R

the previous value of P or R register will be used.

AM79C987 データシート(PDF) 8 Page - Advanced Micro Devices

AM79C987 データシート(HTML) 8 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

データシートダウンロード