データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

AM79C987 データシート(PDF) 10 Page - Advanced Micro Devices

部品番号 AM79C987
部品情報  Hardware Implemented Management Information Base (HIMIB) Device
PDF  30 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  AMD [Advanced Micro Devices]
ホームページ  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C987 データシート(HTML) 10 Page - Advanced Micro Devices

Back Button AM79C987 Datasheet HTML 6Page - Advanced Micro Devices AM79C987 Datasheet HTML 7Page - Advanced Micro Devices AM79C987 Datasheet HTML 8Page - Advanced Micro Devices AM79C987 Datasheet HTML 9Page - Advanced Micro Devices AM79C987 Datasheet HTML 10Page - Advanced Micro Devices AM79C987 Datasheet HTML 11Page - Advanced Micro Devices AM79C987 Datasheet HTML 12Page - Advanced Micro Devices AM79C987 Datasheet HTML 13Page - Advanced Micro Devices AM79C987 Datasheet HTML 14Page - Advanced Micro Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 30 page
background image
AMD
P R E L I M I N A R Y
10
Am79C987
For P = 0 (Repeater Registers), the following registers
are accessible:
R[4:0]
Register
10
Source Address Match (6-byte)
12
Total Octets (4-byte)
13
Transmit Collisions (4-byte)
16
Configuration Register
28
Version/Device ID
30
IMR+ Management Port Set Register
31
IMR+ Management Port Get Register
Register 12 and 13 are 4 bytes long and their contents
are read in the least to most significant byte order.
Register 10 is 6 bytes long and can be read as well as
written to in the least to most significant byte order.
Port Status Registers are organized as follows (P = 1):
R[4:0]
Register
0
TP (Twisted Pair) Ports Partition Status Change
1
AUI Port Partition Status Change
2
TP Link Status Change
3
AUI Loop Back Error
4
Reserved
5
AUI SQE Test Error
6
TP Source Address Change
7
AUI Source Address Change
8
TP Source Address Match Status
9
AUI Source Address Match Status
Port Control Registers are organized as follows (P = 2):
R[4:0]
Register
0
TP Partition Change Interrupt Enable
1
AUI Partition Change Interrupt Enable
2
TP Link Status Change Interrupt Enable
3
AUI Loop Back Error Interrupt Enable
4
Reserved
5
AUI SQE Test Error Interrupt Enable
6
TP Source Address Change Interrupt Enable
7
AUI Source Address Change Interrupt Enable
For other valid port numbers (P in the range 16...23 or
31), the following Attribute Registers are available:
R[4:0]
Register
0
Readable Frames
1
Readable Octets
2
Frame Check Sequence Errors
3
Alignment Errors
4
Frames Too Long
5
Short Events
6
Runts
7
Collisions
8
Late Events
9
Very Long Events
10
Data Rate Mismatches
11
Auto Partitions
12
Source Address Changes
13
Reserved
14
Last Source Address
Registers 0 through 12 are 4 bytes long and their con-
tents are read in the least to most significant byte order.
Register 14 is 6 bytes long and can be read as well as
written to in the least to most significant byte order.
Note that the contents of all attribute registers are main-
tained during an external reset. At power up, the values
of all 4- and 6-byte attributes are random.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com