AM79C987 datasheet(13/30 Pages) AMD

13 / 30 page

AMD

P R E L I M I N A R Y

Am79C987

Transmit Collisions

P[4:0] = 0, R[4:0] = 13

Byte 0

Byte 1

Byte 2

Byte 3

bit 7

bit 31

bit 0

bit 24

MSB

LSB

D Port Read

Transmit Collisions is a 4-byte read-only attribute that

counts the number of transmit collisions this repeater

has detected. The value of the Transmit Collisions at-

tribute is a 32-bit counter with a minimum rollover time of

15 hours.

The 4 bytes in this attribute are sequentially accessed

by reading the D Port, least significant byte first. Note

that once the C Port is programmed for access to this at-

tribute, reading the D Port causes the value of this regis-

ter to be copied to the internal holding register. The data

is then read from the holding register, without affecting

this attribute. This sequence is repeated when the last

byte is read and the D Port is accessed.

Configuration Register

P[4:0] = 0, R[4:0] = 16

This is a read/write register. The value read is the same

as that written. Only zeros should be written into unused

bits. All bits are cleared upon reset.

D Port Read/Write

MSB

LSB

Enable Interrupts. When this bit is set to 0, all inter-

rupts from this HIMIB device are masked (but not

cleared) and the

INT output pin is forced to inactive

state (not driven).

E Interface Error Interrupt Enable. When this bit is set

to 1, the HIMIB device generates an interrupt if the

IMR+ interface is not functioning correctly.

S Source Address Match Interrupt Enable. When this

bit is set, the HIMIB chip will generate an interrupt if

the Source Address of the received packet matches

that programmed into the Source Address Match

M MAC Interface Mode Enable. When this bit is set to 1,

the HIMIB device is assumed to be interfaced to an

802.3/Ethernet MAC Controller. In this mode only

statistics for port 31 (AUI) are valid. The Expansion

Port interface statistics are reported for port 31

(AUI). The HIMIB chip must be kept in this mode until

an external reset occurs.

When the HIMIB chip is interfaced to a MAC device,

such

AMD’s

LANCE

(Am7990)

and

MACE

(Am79C940) etc., the CRS pin from the MAC device

should be connected to the CRS pin of the HIMIB chip.

Also, the SO input pin of the HIMIB chip should be tied

HIGH. Note that in this mode, the HIMIB chip will report

an Interface Error in the Status Register since there is no

connection to the Management Port. Therefore, it is rec-

ommended that the Interface Error Interrupt is left dis-

abled. Certain attributes specific to the Repeater

Management Standard, such as bit rate error, AUI loop-

back error etc., will have no meaning.

Note: Once this bit is set by software, it should not be

cleared again as this may cause incorrect device

operation.

Version and Device ID Register

P[4:0] = 0, R[4:0] = 28

This is a read only register. The 8-bit read has the follow-

ing format:

D Port Read

MSB

LSB

V Version. These bits contain the HIMIB chip version

code. Software may interrogate these bits to deter-

mine additional features that may be available with

future versions of the device. The original version is

0000.

D Device ID. The HIMIB device detects the Repeater

version upon reset. This field is updated to report the

type of physical repeater attached to the HIMIB

device.

Device

IMR chip (Does not support all

attributes)

IMR+ chip

2–15

Reserved for future use

Note: If the HIMIB chip detects an interface error upon

reset, then this field may not contain valid data.

IMR+ Management Port Set Register (S)

P[4:0] = 0, R[4:0] = 30

D Port Write

MSB

LSB

This is a write only register. This register is used for

sending a Set command to the IMR+ device. When a

byte is written to this register, the HIMIB chip will serial-

ize and transfer this byte to the IMR+ Management port.

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