GENNUM CORPORATION

522 - 41 - 08

6 of 14

Fig. 6 Intrinsic Jitter - Pseudorandom (2

Fig. 7 Intrinsic Jitter - Pathological SDI Checkfield

Fig. 8 Typical Input Jitter Tolerance (Characterized)

DETAILED DESCRIPTION

The GS9035A receives either a single-ended or differential

PECL serial data stream at the DDI and DDI inputs. It locks

an internal clock to the incoming data and outputs the

differential PECL retimed data signal and recovered clock

on outputs SDO/SDO and SCO/SCO respectively. The

timing between the input, output, and clock signals is

shown below.

Fig. 10 Input/Output Clock Signal Timing

The GS9035A reclocker contains four main functional

blocks: the Phase Locked Loop, Auto/Manual Data Rate

Select, Frequency Acquisition, and Logic Circuit.

1. PHASE LOCKED LOOP (PLL)

The Phase Locked Loop locks the internal PLL clock to the

incoming data rate. A simplified block diagram of the PLL is

shown below. The main components are the VCO, the

phase detector, the charge pump, and the loop filter.

0

200

400

600

800

1000

1200

1400

1600

1800

2000

100

200

300

400

500

600

SDI DATA RATE (Mb/s)

Max

Typical

Min

Typical Range, Characterized

0

200

400

600

800

1000

1200

1400

1600

1800

2000

100

200

300

400

500

600

SDI DATA RATE (Mb/s)

Typical

Min

Max

Typical Range, Characterized

0

0.1

0.2

0.3

0.4

0.5

0.6

100

200

300

400

500

600

DATA RATE (Mb/s)

0.200

0.250

0.300

0.350

0.400

0.450

0.500

0.550

0.600

0

1020

3040

5060

70

TEMPERATURE (C˚)

143Mb/s

177Mb/s

270Mb/s

360Mb/s

540Mb/s

DDI

SDO

SCO

50%