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5. LOCKING

The GS9035A indicates lock when three conditions are

satisfied:

1. Input data is detected.

2. The incoming data signal and the PLL clock are phase

locked.

3. The system is not locked to a harmonic.

The GS9035A defines the presence of input data when at

least one data transition occurs every 1µs.

The GS9035A assumes that it is NOT locked to a harmonic

if the pattern ‘101’ or ‘010’ (in the reclocked data stream)

recommended component values, this corresponds to

approximately 150µs. (In an harmonically locked system, all

bit cells are double clocked and the above patterns

become ‘110011’ and ‘001100’, respectively.)

5.1 Lock Time

The lock time of the GS9035A depends on whether the

input data is switching synchronously or asynchronously.

Synchronous switching refers to the case where the input

data is changed from one source to another source which is

at the same data rate (but different phase). Asynchronous

switching refers to the case where the input data to the

GS9035A is changed from one source to another source

which is at a different data rate.

When input data to the GS9035A is removed, the GS9035A

latches the current state of the counter (divider modulus).

Therefore, when data is reapplied, the GS9035A begins the

lock procedure at the previous locked data rate. As a result,

in synchronous switching applications, the GS9035A locks

very quickly. The nominal lock time depends on the

switching time and is summarized in the table below:

In asynchronous switching applications (including power

up) the lock time is determined by the frequency acquisition

circuit as described in section 2, Frequency Acquisition. In

manual mode, the frequency acquisition circuit may have to

sweep over an entire cycle (depending on initial conditions)

cycle through 5 possible counter states (depending on

for the GS9035A operating in a typical SMPTE 259M

application is approximately 1.3ms.

The GS9035A has a dedicated LOCK output (pin 3)

indicating when the device is locked. It should be noted

that in synchronous switching applications where the

switching time is less than 0.5µs, the LOCK output will NOT

be de-asserted and the data outputs will NOT be muted.

5.2 DVB-ASI

Design Note: For DVB-ASI applications having significant

instances of few bit transitions or when only K28.5 idle bits

are transmitted, the wide-band PLL in the GS9035A may

lock at 243MHz being the first 27MHz sideband below

270MHz. In this case, when normal bit density signals are

transmitted, the PLL will correctly lock onto the proper

270MHz carrier.

TABLE 3: Data Rate Select in Manual Mode

AUTO/MAN = 0 (Manual Mode)

SMPTE

SS[2:0]

DIVIDER

MODULI

PLL CLOCK

1

000

4

1

001

2

1

010

2

1

011

1

1

100

1

1

101

8

1

110

8

1

111

-

-

0

000

4

0

001

4

0

010

2

0

011

2

0

100

1

0

101

1

0

110

8

0

111

-

-

TABLE 4: Lock Time Relative to Switching Time

SWITCHING TIME

LOCK TIME

<0.5µs

10µs

0.5µs - 10ms

> 10ms