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CS98200-EB データシート(PDF) 49 Page - Cirrus Logic

部品番号 CS98200-EB
部品情報  New Highly-Integrated Processor for Tommorrow DVD Players and DVD Receivers
PDF  60 Pages
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メーカー  CIRRUS [Cirrus Logic]
ホームページ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS98200-EB データシート(HTML) 49 Page - Cirrus Logic

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Copyright 2002 Cirrus Logic (All Rights Reserved)
49
CS98200
Next Generation DVD Processor
8. INTERFACE DESCRIPTIONS
8.1
SDRAM Interface Pins
These pins are used to interface the CS98200 with some external SDRAM. The CS98200 can interface
with SDRAM of various sizes. Only 32-bit data width is supported. Follow the instructions in Table
15 on how to interface with any particular configuration of SDRAM.
8.2
ROM/NVRAM Interface Pins
This is the interface to the non-volatile memory that contains the firmware. See Table 16. It could be
either ROM, NVRAM – FLASH, or EEPROM, or any combination of these types of memory. This
interface can also connect to SRAM that would emulate a ROM on a development system. The bus
width is 8 bits.
Pin
Signal Name
Type
Description
11,12,13,15,16,
17,18,20,21,23,
26,27,28,29,30,
32,61, 56, 55,
53, 51, 50, 49,
48, 47, 45, 42,
40, 39, 38, 37,
36,
M_D[31:0]
B
Memory Data Bus. CS98200 uses all 32 bits.
90, 89, 88, 87,
85, 82, 80, 79,
78, 77, 76
M_A[10:0]
O
Memory Address Bus. Connect in order starting with M_A[0] to
all RAM address pins not already connected to M_BS[1:0]_N
or M_AP.
64
M_CKO
O
Memory Clock
66
M_CKE
O
Memory Clock Enable
69
M_BS0_N
O
Bank Selection. Always connect to RAM BS or BS0 pin.
68
M_BS1_N
O
Bank Selection. Always connect to RAM BS or BS0 pin.
67
M_AP
O
Memory Auto Pre-charge. Always connect to RAM AP pin.
70
M_RAS_N
O
Memory Row Address Strobe
71
M_CAS_N
O
Memory Column Address Strobe
73
M_WE_N
O
Memory Write Enable
62, 35, 33, 10
M_DQM[3:0]
O
IO Mask of Data Bus M_DQM[3] -> M_D[31:24]
Table 15. SDRAM Interface Pins
Pin
Signal Name
Type
Description
91,92,93,94,95,
96,99,101
NV_D[7:0]
B
Memory Data Bus.
90, 89, 88, 87,
85, 82, 80, 79,
78, 77, 76
M_A[10:0]
O
Memory Address Bus[10:0]
32, 30, 29, 28,
27, 26, 23, 21,
20, 18, 17, 16
M_D[31:16]
O
Memory Address Bus[23:11]
67
M_AP
O
Output Enable
73
M_WE_N
O
Write Enable.
Table 16. ROM/NVRAM Interfa c e



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