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NTP53X2 データシート(PDF) 39 Page - NXP Semiconductors |
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NTP53X2 データシート(HTML) 39 Page - NXP Semiconductors |
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39 / 133 page  NXP Semiconductors NTP53x2 NTAG 5 link - NFC Forum-compliant I2C bridge NTP53x2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 3.3 — 3 July 2020 COMPANY PUBLIC 544533 39 / 133 Table 57. Event Detection Clear Register Location (ED_INTR_CLEAR_REG) Block Address NFC I2C Byte 0 Byte 1 Byte 2 Byte 3 ABh 10ABh ED_INTR_ CLEAR_REG RFU Table 58. Event Detection Clear Register (ED_INTR_CLEAR_REG) Bit Name Value Description 7 to 1 RFU all 0b 0 ED_INTR_CLEAR 1b write 1b to release ED pin ED pin is cleared i.e. released when writing 01h to the ED clear register. The bit gets automatically cleared after clearing the ED pin. 8.1.3.20 I2C slave configuration settings I2C slave functionality can be configured with the following configuration registers from both interfaces. Table 59. I2C Slave Configuration Location Block Address NFC I2C Byte 0 Byte 1 Byte 2 Byte 3 3Eh 103Eh I2C_SLAVE_ADDR I2C_SLAVE_CONFIG I2C_MASTER_ SCL_LOW I2C_MASTER_ SCL_HIGH Table 60. I2C Slave Configuration Definition (I2C_SLAVE_ADDR) Bit Name Value Description 7 RFU 0b 6 to 0 I2C_SLAVE_ADDR 54h I2C slave address used in slave configuration Table 61. I2C Slave Configuration Definition (I2C_SLAVE_CONFIG) Bit Name Value Description 7 to 3 RFU 00000b 0b Slave does not reset if repeated start is received (Default) 2 I2C_S_REPEATED_START 1b I2C slave resets internal state machine on repeated start 1 RFU 0b 0 RFU 0b 8.1.3.21 I2C master clock configuration settings I2C Master baud rate and SCL high and low can be configured by the related configuration values. Details about the formula can be found in I2C master section. |
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